JPS6366441B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a high-frequency transistor internal matching circuit provided in, for example, a high-frequency, high-output transistor of a multi-cell parallel operation type. Generally, the input/output impedance of high frequency, high output transistors is extremely low and may be less than 1Ω. Such low impedance transistors
A high impedance transformation ratio is required to match transmission components such as 50Ω systems. Furthermore, as the operating frequency increases, the influence of parasitic elements in the transistor envelope cannot be ignored, and it is difficult to obtain a practical bandwidth while achieving a high impedance transformation ratio with a matching circuit provided outside the envelope. becomes difficult. A so-called internal matching technique has been proposed to overcome these drawbacks, and this technique is widely used. This internal matching technique is a method of forming part of the matching network inside the envelope and obtaining the required impedance transformation ratio and bandwidth through the external matching network while reducing the effects of the package's parasitics. It is. FIG. 1 shows an equivalent circuit of, for example, a base-grounded high-frequency transistor using such an internal matching technique. In the figure, 11 is a transistor, 12
~14 are input/output terminals of the transistor, and 1
2 is an emitter, 13 is a base, and 14 is a collector. Further, 15 is an inductor, 16 is a capacitor, and 17 is a parasitic element of the envelope. Also, the internal matching circuit on the output side is the base 13 of the transistor 11.
A DC blocking capacitor 2 connects an inductor 19 that resonates in parallel with the capacitor 18 existing between the
A common method is to provide the impedance at the output terminal of the envelope with a value close to the output operating resistance of the transistor 11. Furthermore, as shown in Fig. 2, high-frequency, high-output transistors that have been put into practical use have been designed to improve heat dissipation by dividing the junction of the transistor into a number of cells 21 to disperse the heat generating parts. A long and thin transistor pellet 22 is made in which the cells 21 can be arranged in parallel in a straight line so that each cell 21 operates uniformly, and a capacitor 23 of a MOS (metal oxide) semiconductor structure, a bonding wire 24 or a patterned conductor 25 is made. The used inductor is used to form an internal matching circuit inside the envelope. In addition, in the figure, 26 is the collector land, which is the mounting part of the transistor pellet 22, and 27 is the collector land.
28 is an emitter input terminal, and 29 is a collector output terminal. Reference numeral 30 denotes a substrate of the envelope, which is made of ceramic with low thermal resistance such as beryllia (BeO). Further, 31 is a side wall of the envelope, which is made of an insulating material such as alumina. Now, the output side internal matching inductor 19 shown in FIG. 1 corresponds to both ends of the collector land 26 and the DC blocking capacitor (FIG. 1 20) as shown in FIG. 2 due to the dimensional limitations of the envelope. A patterned conductor 25 is formed between the MOS capacitor 23 and the ground conductor portion 27. For this reason, the matching state differs between cells at the ends of the elongated transistor pellet 22 and cells near the center. This is because the inductance between both ends of the collector land 26 cannot be ignored compared to the value of the matching inductor 19, that is, the inductance value of the conductor 25. Such adverse effects become more pronounced when the number of cells is increased for the purpose of increasing output or when the frequency used is high. Therefore, with the internal matching circuit as shown in FIG. 2, there is a limit to the ability to increase the output power and frequency of the transistor, and it has not been possible to improve the performance of the transistor. The present invention was made in view of the above circumstances, and
By making the operating state of each cell of a multi-cell parallel-operating high-frequency transistor as uniform as possible, we have created a high-frequency transistor internal matching circuit that can realize high-frequency transistors with higher output and higher efficiency than conventional transistors even when using the same transistor pellet. This is what we provide. Hereinafter, one embodiment of the present invention will be described with reference to the drawings. As described above, if the inductance between both ends of the collector land 26 in FIG. 2 can be made sufficiently smaller than the value of the matching inductor 19, the operating state of each cell 21 can be made uniform.
According to electromagnetism, the method of reducing the inductance between both ends of the collector land 26 is to widen the width of the collector land 26 or reduce the thickness of the substrate 30. Incidentally, the document “Microstrip Lines for
Microwave Integrated Circuit”BSTJ 48.
According to P.1421. (1969), when a microstrip line with a width W is formed on a substrate with a thickness H and a relative permittivity εs, the characteristic impedance Zo of the line is
and the wavelength shortening rate λ/λg (λ: free space wavelength, λg: line wavelength) is is given by On the other hand, the values of inductance and capacitance per unit length of this line are △L, △
If we set it as C,

[Formula] λ/λg=C√△・△, C: Given by the speed of light. From these relationships, the inductance ΔL and capacitance ΔC per unit length are determined by the following equations. △L=120 ₁ π/C [W/H+2.42−0.44H/W+(1
-H/W) ⁶ ] △C=ε・ff/120π・C [W/H+2.42−0.44H/
W+(1-H/W) ⁶ ] In other words, if the width W of the collector land 26 can be increased or the thickness H of the substrate 30 can be made sufficiently thin, the inductance between both ends of the collector land 26 can be made smaller than the value of the matching inductor 19. It turns out that it can be made sufficiently small. However, increasing the width of the collector land 26 increases the size of the envelope, which is not a good idea. Therefore, in the present invention, in order to reduce the inductance between both ends of the collector land 26, as shown in FIG.
In parallel with this, a pseudo collector land 32 as a line piece to be described later is provided, and a bonding wire 24 or the like connects the collector land 26→pseudo collector land 32→
A patterned conductor 25 wired with the collector output terminal 29 and corresponding to an output side matching inductor
Both ends of the pseudo collector land 32 and the ground conductor part 2
7 and corresponds to a DC blocking capacitor.
This can be realized by wiring with a bonding wire 24 or the like via the MOS capacitor 23. The above-mentioned pseudo collector land 32 has a MOM structure or MOS electrode structure of a conductor layer-insulator layer-conductor layer, and the thickness of the insulator layer can be up to about 1 μm by forming it by a method such as vapor deposition. Can be made thinner. By doing so, the inductance of the pseudo collector land is added in parallel to the inductance of the collector land, so that the overall inductance is reduced. Therefore, the value of the output internal matching inductor, that is, the inductance value of the conductor 25, can be made sufficiently small.
Each cell 21 on the pellet 22 can be operated uniformly. Note that by reducing the thickness of the insulating layer of the pseudo collector land 32, the capacitance between the collector of the transistor and the ground conductor portion 27 increases. In this embodiment, the capacitance between the collector and base of the transistor pellet 22 is 64 pF, and the capacitance of the pseudo collector land 32 is 16 pF, so the total capacitance is 80 pF, which is a 25% increase compared to the conventional one. However, the inductance between both ends of the pseudo collector land 32 can be easily reduced to 0.1 nH or less (in this example, approximately
0.04nH), the inductance between both ends of the collector land 26 in the conventional example is approximately
It can be reduced to less than 1/10 compared to 1.4nH. The table below shows a comparison of characteristics between a conventional transistor made using the same transistor pellet and the transistor of this embodiment.

[Table] From the table above, the transistor of this example has an output of
It can be seen that the performance is improved by 5% at 10W and efficiency compared to the conventional transistor. In addition, in Figure 3, 2
8, 29, and 31 are an emitter input terminal, a collector output terminal, and an envelope side wall, respectively, similar to those shown in FIG. As explained above, according to the present invention, the operating states of a large number of cells of internally matched high-frequency, high-output transistors operating in parallel are made uniform,
It is possible to provide a high-frequency transistor internal matching circuit that can realize high-frequency transistors with higher output and higher efficiency than conventional ones. Note that if the insulator layer of the pseudo collector land is made thicker or wider, the inductor of the pseudo collector land becomes larger, but the inductor of the pseudo collector land is added parallel to the inductor of the collector land. There is no change in this fact, so the inductor of the collector land will be reduced compared to the conventional one. That is, irrespective of the shape of the pseudo collector land, by connecting the pseudo collector land to the collector land, each cell on the pellet can be operated uniformly.

[Brief explanation of drawings]

Figure 1 is an equivalent circuit diagram of a high-frequency, high-output transistor with an internal matching circuit, Figure 2 a is a front view of a conventional transistor with an internal matching circuit, and Figure 2 b is a cross-sectional view taken along line BB in Figure a. 3A is a front view showing a transistor with an internal matching circuit to which an embodiment of the present invention is applied, and FIG. 3B is a sectional view taken along line BB in FIG. 3A. 11...Transistor, 12...Emitter terminal, 1
3...Base input terminal, 14...Collector output terminal,
22...Transistor pellet, 24...Bonding wire, 32...Pseudo collector land.

Claims (1)

[Claims] 1 Input/output terminals, grounding conductor, and parallel operation multi-cell
In a high-frequency transistor internal matching circuit provided inside a transistor envelope having a transistor pellet mounting conductor, a MOM structure (conductor layer-insulator layer-conductor layer) or MOS (metal oxide A line piece having an electrode structure is mounted in parallel with the pellet mount conductor, and the upper electrode of this line piece is connected to the pellet mount conductor and the output terminal, and the upper part of the line piece is connected to the pellet mount conductor and the output terminal. A high-frequency transistor internal matching circuit characterized by connecting an output matching inductor to both ends of the electrode.