JPS6365365A - Ultrasonic flaw detection device - Google Patents

Abstract

PURPOSE:To detect the flaw of an extremely thin sample and its surface defect by providing a circuit which operates with a rigger signal outputted when a sent pulse exceeds a set threshold value and delays an RF signal by an optional set time. CONSTITUTION:When the level of the sent pulse from a probe exceeds the set threshold value, a delay trigger circuit 14 operates to set the pulse width of a delay trigger and then when a surface echo S exceeds the threshold value, the delay circuit 15 and a gate circuit 16 operate to start a sequence wherein the signal is delayed by the set pulse width and respective pulses of the gate are outputted. The RF signal received by a receiving circuit, on the other hand, is inputted to an RF delay circuit 22 through an input circuit 9, but the moment the level of the sent pulse exceeds the threshold value, the circuit 22 is operated with the trigger signal outputted by a trigger circuit 10 to select a delay terminal so that the defect echo in the RF signal inputted to the circuit appears only within the pulse width of the gate. Consequently, the signal is delayed by the optionally set desired time and outputted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an ultrasonic flaw detection device for inspecting internal defects in materials or products, and in particular, for inspecting objects such as metal materials, ceramics, ICs, etc. near the surface or at the poles). This is a flaw detection device suitable for inspecting minute defects inherent in 1 to +A.

[Conventional technology]

In materials and industrial products, it has been conventional to detect internal defects in so-called thin materials, and even if the thickness is not so thin, defects that exist near the surface of the object (hereinafter referred to as surface defects). It has been widely implemented in various technical fields. In order to demonstrate much higher performance and functionality than conventional methods for new materials and electronic products, the above-mentioned flaw detection is required to reliably detect surface defects and minute defects even closer to the surface. It's coming.

A conventional general flaw detection device will be explained with reference to FIGS. 5 to 7. Figure 5 is an explanatory diagram of the structure of the flaw detection device, where ■ indicates water 2
3 is a thin specimen placed at the bottom of the water tank 1, and 4 is a probe immersed in water 2. 5 is a pulse emitting circuit that causes the probe 4 to emit ultrasonic pulses; 6 is the surface of the object 30;

A receiving circuit 7' is a receiving circuit 6 which receives and amplifies the RF multiplied signal of the reflected wave reflected from the defect and the bottom surface via the probe 4.
8 is an oscilloscope that displays the waveform output from the peak detector 7'.

FIG. 6 is a circuit diagram of the peak detector 7', where 9 is the R of the reflected wave amplified by the receiving circuit 6.
An input circuit into which the F signal is input; 10 is a trigger circuit; 11
is the delay trigger threshold (setting circuit) that sets the threshold for starting the pulse of the delay trigger, 12 is the monitor circuit that outputs the output No. 3 of the gate control circuit 18 to the oscilloscope 8, and 13 is the monitor synchronizer. A circuit 14 is a delay trigger circuit for setting the pulse width of the delay trigger that is activated when the level of the transmitting pulse of the probe 4 exceeds the threshold value, and 15 is a delay trigger circuit for setting the pulse width of the delay. A gate circuit 16 is a gate circuit that can set the gate pulse width to any 40 positions and widths, and a gate circuit 16 is connected to the multi-by-break 17 to adjust the delay trigger, delay, and gate pulse widths. l-t:+-le circuit 18
is formed. Is 19 the first output from input circuit 9? 13, the RF detection circuit 20 converts the output signal of the Rr detection circuit 19 into an I) C voltage proportional to its value, and stores it at that value until the gate signal of the iYJ gate control circuit 18 is closed. Peak detection circuit, 21
1) is an output circuit that outputs the C voltage. FIG. 7 is a characteristic diagram of pulses generated when the flaw detection device is used. In the figure (al is an example of the echo pattern of the reflected wave from the object 3, F is the transmitted pulse, S is the surface echo, F is the defect echo, and B is the bottom echo. L is the level of the transmitted pulse T) (b) is the pulse width P7, fc) of the delay trigger set in the delay trigger circuit 14, and the pulse width Pd, td) of the delay set in the delay circuit 15 is - the gate pulse width Pg set in the circuit 16;

As soon as the level of the transmitted pulse T emitted from the probe 4 exceeds the set threshold l, the delay trigger circuit 14
is activated, and the pulse width Pt of the delay trigger is set. Subsequently, when the surface echo S exceeds the threshold, the delay circuit 1
5 and gate circuit 16 are activated to begin the sequence, the pulse width of the delay P.

The gate opens at the same time as closes, and the set pulse intensity p
Close after g has elapsed.

By the way, the current delay circuit 15 with multi-by-break 17
and the minimum pulse width P, which can be set by the gate circuit 16.
, is approximately 80 ns, and the propagation delay time of the multivibrator 17 is approximately 40 ns on average depending on the configuration of the device. The minimum value of the pulse width P6 of the delay between starting the pulse of The defect echo I? cannot appear within the gate pulse width P shown in figure td).The propagation distance is approximately 350 μm in the case of steel+A, for example, from the surface of the object 3 to the defect. Unless the distance is approximately 350 pm or more, the defective echo F cannot appear within the gate pulse width Pg.In this way, with the circuit configuration described above, it is possible to cause the defective echo F to appear within the thick pulse width Pg of the object 3. Force\Subject 3
When inspecting minute surface defects very close to the surface of the object, or minute defects inherent in extremely thin materials such as 200 to 300 μm thick, the surface echo S is the defect echo F.
appear very close to each other, the defect echo F has a pulse width P of the gate.

It cannot be made to appear inside. In addition, when the object 3 to be inspected is the above-mentioned steel material, the distance from the surface to the defect is 350 μm.
m or more, and the defect echo F has a gate pulse width of 2 g.
Even if the surface defect appears within the propagation delay time, if the surface defect is close enough to the surface that it appears within the propagation delay time, it is effectively gated for the above reason, and the defect echo F is detected in both cases. I can't. Therefore, it has been a problem that surface defects at such positions and defects inherent in extremely thin materials cannot be detected even though the defects exist.

[Problem that the invention seeks to solve]

As mentioned above, in conventional ultrasonic flaw detection equipment, the minimum pulse width that can be set in the delay circuit and gate circuit is approximately 80 mm.
ns, it is impossible to detect defects on the surface of the test object or defects inherent in the test object made of ultra-thin material. Furthermore, since it was not possible to apply a gate to only defect echoes at a desired arbitrary depth, there was a problem in that it was not possible to detect each defect when multiple defects were present close to each other in the thickness direction. was.

The present invention solves the above-mentioned problems of the prior art, and makes it possible to detect ultrathin specimens and surface defects, as well as to detect multiple defects that are adjacent to each other in the thickness direction and that contain "C". It is an object of the present invention to provide an ultrasonic flaw detection device that can arbitrarily detect each defect.

[Means for solving problems]

The present invention includes a pulse generation circuit that connects to a probe facing a subject in a liquid tank and applies a transmission pulse, a receiver circuit that receives an RF signal of a reflected wave from the subject, and a delay circuit. Delay trigger circuit that sets the trigger pulse width, Delay circuit that sets the delay pulse width after the delay trigger pulse closes, Delay trigger threshold setting that sets the threshold for raising the delay trigger and delay pulse. A trigger circuit that emits a trigger signal when the transmitted pulse or the echo level of the reflected wave from the object exceeds a set threshold;
and an input circuit in which each circuit of the gate circuit that sets the pulse width of the gate is connected to a multi-by-break that generates a pulse set respectively in each circuit, and the RF multiplied signal received by the receiving circuit is inputted; A peak detector has an RF detection circuit that detects the RF (g) output from the input circuit and outputs a voltage proportional to the peak value of the detected RF signal, and displays the output waveform of the peak detector. In an ultrasonic flaw detection device equipped with an oscilloscope, when the transmitted pulse exceeds the threshold,
An RF delay circuit is provided which is activated by a trigger body array output from the trigger circuit and delays the RF multiplied signal output from the input circuit by an arbitrarily set time, and the delayed R
The ultrasonic flaw detection apparatus described above is equipped with a peak detector configured to input an F-fold signal to the RF detection circuit, so that an extremely thin material can be tested.

[Effect]

When the pulse width of the transmitted pulse emitted from the probe exceeds the set threshold, the delay trigger circuit operates to set the pulse width of the delay trigger, and then the surface echo S exceeds the threshold. When the value is exceeded, a sequence begins in which the delay circuit and gate circuit operate to output delay and gate pulses of the set pulse width. On the other hand, the RF4# signal received by the receiving circuit is input to the RF delay circuit via the input circuit, but the RF delay circuit receives the signal from the trigger circuit as soon as the level of the transmission pulse exceeds the threshold. an RF multiplied signal activated by the output trigger signal and manually input into the circuit;
The delay terminals were selected and arbitrarily set so that the defective RF multiplied signal ':1- appeared within the pulse width of the gate: il(,') l+,'1 The output is delayed by a certain amount of time.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 1 to 4. In the figures, the same reference numerals as in FIGS. 5 to 7 indicate the same things. FIG. 1 is a main block circuit diagram of a peak detector, FIG. 2 is a characteristic diagram thereof, FIG. 3 is a diagram showing a specific example of the configuration of an RF delay circuit, and FIG. 4 is a characteristic diagram thereof.

Reference numeral 22 denotes an RF delay circuit to which the RF multiplied signal received by the receiving circuit 6 is input via the input circuit 9. When the level of the transmission pulse T exceeds a threshold, the circuit 22 activates the trigger circuit 1.
It is activated by the trigger signal output from 0, and the RF multiplied signal is delayed by an arbitrarily set time and then output, and the defective echo F
This is a circuit designed to make the following appear within the gate pulse.

7 is a peak detector having the above circuit configuration. RI in Figure 3? An example in which an inductor is used as the delay circuit 22 will be shown. In this case, the delay time in the RF delay circuit 22 is determined by the number of turns of the coil, that is, 1/'H]C of the inductance H and the conductance C. −
can be arbitrarily selected within the range. Figure 4 is the third
This is a characteristic diagram showing a delay situation corresponding to a plurality of delay terminals shown in the figure, and is a characteristic diagram when three terminals a, b, and c are sequentially provided from an input terminal IN to an output terminal OUT.

As the number of turns of the coil increases, the value of 1i-c-- increases, so the RF multiplied signal waveform is delayed by the time td+ from the position shown in Figure 4 (IN) to terminal a in the same figure (not shown in al). The output terminal OUT reaches the position delayed by a time t, .□.

Therefore, by selecting the terminal, the delay time can be set arbitrarily.

As mentioned above, in the case of surface defects and defects inherent in extremely thin materials, the defect echo F appears very close to the surface roughness: 1-8, as shown in Fig. 2 (8) as an example. It becomes an echo pattern like this. When the level of the transmission pulse T emitted from the probe f exceeds the threshold, the delay trigger circuit 14 is activated and the pulse width P shown in the 21st phase (bl) is activated.
1 delay trigger pulse is set, and when the surface echo S exceeds the threshold 11r+1 after time t, the delay circuit 15
A delay pulse of the same figure (pulse width P, not shown in C1) set in the same figure is output.Subsequently, at the same time as the delay pulse width Pa closes, A gate pulse with a pulse width P is output. However, as shown in the figure, at the same output position of the gate pulse as in the conventional case, the position is shifted and the defective echo F cannot be gated for a long time as in the conventional case. Therefore, as shown in te+ in the same figure, the RF delay circuit 22 is activated by the trigger signal (pulse width PT) output from the trigger circuit 10 at the same time that the level of the transmission pulse T exceeds the threshold value, and the RF delay circuit 22 is activated to generate the RF multiplied signal. The waveform is output after being delayed by the time t6 set in the circuit 22. Therefore, the position where the surface echo S exceeds the threshold is the sum of the time t8 and the time t4 set in the RF delay circuit 22. T'tf'l (1, +1.), and the defective echo F can appear within the pulse width P8 of the gate.

The time t can be arbitrarily set according to the echo patterns of the surface echo S and the defect echo F, the delay pulse width P6 and the gate pulse width P, etc., which are set according to the echo patterns. 1- It becomes possible to apply the thickness of the object to be inspected, as well as to a single defect where S and defect echo F appear close to each other. For example, in the case of an echo pattern in which defect echoes Ft, Ft, and Fs are close to each other, the delay terminals are selected in order from a and each defect is gated in order by setting the corresponding time t6 for flaw detection. be able to.

(Effects of the Invention) As explained above, the present invention provides an ultrasonic flaw detector equipped with 18 pulse generating circuits and a receiving circuit connected to a probe facing a subject in a liquid tank, a peak detector, and an oscilloscope. In the apparatus, within the peak detector,
We installed an RF delay circuit that is activated by the trigger signal output from the trigger circuit when the transmitted pulse exceeds a set threshold, and delays the RF multiplied signal by an arbitrarily set time. It is possible to detect defects in the object and surface layer to shallow positions that were previously impossible, and it is also possible to detect multiple defects that are close to each other in the thickness direction of the object and are within °C, and can be detected with high accuracy. It has excellent practical effects.

[Brief explanation of the drawing]

1 to 4 are explanatory diagrams of embodiments of the present invention, in which FIG. 1 is a main block circuit diagram of a peak detector, FIG. 2 is a characteristic diagram thereof, and FIG. 3 is a concrete diagram of an RF delay circuit. FIG. 4 is a diagram showing a typical configuration example, and is a characteristic diagram thereof. FIG. 5 is an explanatory diagram of the configuration of an ultrasonic flaw detection device, FIG. 6 is a main block circuit diagram of a conventional peak detector, and FIG. 7 is a characteristic diagram thereof. Patent Applicant Hitachi Construction Machinery Co., Ltd. Agent Patent Attorney Tadashi Akimoto No. 1 Figure 72-7 Gold 7゜ Figure 2 Figure 3 Terui Tokikoko No. 4Y! i! J Figure 5 Figure 6 and . b7te4↑7da

Claims (1)

[Scope of Claims] 1. A pulse transmitting circuit that is connected to a probe facing a subject in a liquid tank and applies a transmission pulse, and a receiving circuit that receives an RF signal of a reflected wave from the subject; A delay trigger circuit that sets the pulse width of the delay trigger, a delay circuit that sets the pulse width of the delay after the pulse of the delay trigger closes, a delay trigger threshold that sets the threshold for raising the delay trigger and the pulse of the delay. Each circuit includes a setting circuit, a trigger circuit that issues a trigger signal when the echo level of a transmitted pulse or a reflected wave from the object exceeds a set threshold, and a gate circuit that sets the gate pulse width. It has an input circuit connected to a multivibrator that generates a set pulse, and into which the RF signal received by the receiving circuit is input, and an RF detection circuit that detects the RF signal output from the input circuit. In an ultrasonic flaw detection device equipped with a peak detector that outputs a voltage proportional to the peak value of the detected RF signal and an oscilloscope that displays the output waveform of the peak detector, when the transmitted pulse exceeds the threshold value. , an RF delay circuit is provided which is activated by a trigger signal output from the trigger circuit and delays the RF signal output from the input circuit by an arbitrarily set time, and the delayed RF signal is transmitted to the R
An ultrasonic flaw detection device comprising a peak detector configured to input to an F detection circuit. 2. The ultrasonic flaw detection apparatus according to claim 1, wherein the RF delay circuit is an inductor.