JPS6287854A - Method for ultrasonic flaw detection - Google Patents

Method for ultrasonic flaw detection

Info

Publication number
JPS6287854A
JPS6287854A JP60227007A JP22700785A JPS6287854A JP S6287854 A JPS6287854 A JP S6287854A JP 60227007 A JP60227007 A JP 60227007A JP 22700785 A JP22700785 A JP 22700785A JP S6287854 A JPS6287854 A JP S6287854A
Authority
JP
Japan
Prior art keywords
circuit
gate
pulse
echo
pulse width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60227007A
Other languages
Japanese (ja)
Inventor
Susumu Okikawa
進 沖川
Sakae Takeda
竹田 栄
Yasuo Hayakawa
泰夫 早川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Construction Machinery Co Ltd
Hitachi Ltd
Original Assignee
Hitachi Construction Machinery Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Construction Machinery Co Ltd, Hitachi Ltd filed Critical Hitachi Construction Machinery Co Ltd
Priority to JP60227007A priority Critical patent/JPS6287854A/en
Publication of JPS6287854A publication Critical patent/JPS6287854A/en
Pending legal-status Critical Current

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  • Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)

Abstract

PURPOSE:To certainly inspect the flaw of a surface layer or the fine flaw of an extremely thin material without receiving the effect of a signal propagation delay time between circuits, by operating a gate circuit by the pulse of a surface echo appearing at first after a set pulse width has been closed. CONSTITUTION:A peak detector 7 has a delay trigger circuit 14 setting the pulse width of a delay trigger operated when the lever of a transmission pulse exceeds a threshold value and a gate circuit 16 capable of setting the pulse width of a gate to an arbitrary position and width and detects the peak value of a reflected wave to output voltage proportional to said peak value. The flaw echo of the surface layer flaw close to the surface of an object to be inspected or the fine flaw internally present in an extremely thin material appears in extremely close vicinity to a surface echo. Therefore, when the circuit 14 is operated in such a state that the level of the transmission pulse exceeds the set threshold value and the set pulse width is closed, no delay is applied by the pulse of the surface echo and the circuit 16 is operated by the pulse of the surface echo appearing at first thereafter to open the gate so as to contain the surface echo and the flaw echo in the pulse width of the gate.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は材料または製品の内部欠陥を検査する超音波探
傷方法に関し、特に被検体例えば金属材料、セラミック
ス、IC等の表面近傍や掻薄材に内在する微細な欠陥を
検査するのに好適な探傷方法である。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an ultrasonic flaw detection method for inspecting internal defects in materials or products, particularly in the vicinity of the surface of objects to be inspected, such as metal materials, ceramics, ICs, etc., and thin materials. This is a suitable flaw detection method for inspecting inherent minute defects.

(発明の背景〕 材料または工業製品において、厚さの薄いいわゆる薄材
の内部欠陥や、厚さがそれほど薄くなくてもその被検体
の表面付近に内在する欠陥(以下表層欠陥という)を探
傷することは、従来がらいろいろな技術分野でかなり実
施されている。そして前記探傷は、新しい素材や電子製
品等に対し従来と比較して格段に高い性能、機能を発揮
せしめるため、一層表面に近い表層欠陥や微細な欠陥を
も確実に検出することが要求されてきている。従来の一
般的な探傷装置を用いた探傷方法の1例を第3図ないし
第5図について説明する。第3図は探傷装置の構成説明
図で、1は水2を満たした水槽、3は水槽1内の底に設
置された薄材の被検体、4は水2に浸漬された探触子で
ある。5は探触子4に超音波パルスを発信させるパルス
回路、6は被検体3の表面、欠陥および底面から反射す
る反射波を探触子4を介して受信し増幅する受信回路、
7′は受信回路6で増幅された反射波のピーク値を検波
してその値に比例するDC電圧を出力するピークディテ
クタ、8はピークディテクタ7′から出力された波形を
表示するオシロスコープである。第4図は前記ピークデ
ィテクタ7′の主要ブロック回路図で、9は前記受信回
路6で増幅された反射板のパルスが入力される入力回路
、10はトリガ回路、11は遅延トリガのパルスを立ち
上げるしきい値を設定する遅延トリガしきい値設定回路
、12はモニタ回路、13はモニタシンクロ回路、14
は前記探触子4の送信パルスのレベルが、前記しきい値
を越えたときに作動する遅延トリガのパルス幅を設定す
る遅延トリガ回路、15は遅延のパルス幅を設定する遅
延回路、16はゲートのパルス幅を任意の位置と幅に設
定できるゲート回路で、いずれもマルチプレクサ17に
接続され、遅延トリガ、遅延およびゲートの各パルス幅
を調節するゲートコントロール回路18を形成している
。19は入力回路9に入力されたパルスを検波するRF
稜波回路、20はRF検波回路19の出力信号をその値
に比例するDC’[圧に変換し、前記ゲートコントロー
ル回路18のゲート信号が閉じるまでその値を保持する
ピーク検波回路、21は前記DC電圧を出力する出力回
路である。第5図は前記探傷装置を使用した探傷方法を
説明する特性線図である。図において+8>は被検体3
からの反射波のエコーパターンの1例で、Tは送信パル
ス、Sは表面エコー、Fは欠陥エコー、Bは底面エコー
をそれぞれ示す。Lは送信パルスTのレベルのしきい値
のレベルを示す線である。fb)は遅延トリガ回路14
で設定される連通トリガのパルス幅PL、(C)は遅延
回路15で設定される遅延のパルス幅Pd、(dlはゲ
ート回路16で設定されるゲートのパルス幅P9である
(Background of the Invention) In materials or industrial products, it is used to detect internal defects in so-called thin materials and defects that exist near the surface of the specimen even if the thickness is not so thin (hereinafter referred to as surface defects). This has been carried out quite a lot in various technical fields.In order to enable new materials, electronic products, etc. to exhibit significantly higher performance and functionality than in the past, flaw detection is performed on the surface layer, which is closer to the surface. It has become necessary to reliably detect defects and even minute defects.An example of a flaw detection method using a conventional general flaw detection device will be explained with reference to Figs. 3 to 5. In this diagram, 1 is a water tank filled with water 2, 3 is a thin specimen placed at the bottom of the water tank 1, 4 is a probe immersed in water 2, and 5 is a probe immersed in water 2. A pulse circuit that causes the probe 4 to emit ultrasonic pulses; 6 a receiving circuit that receives and amplifies reflected waves reflected from the surface, defects, and bottom of the object 3 via the probe 4;
7' is a peak detector that detects the peak value of the reflected wave amplified by the receiving circuit 6 and outputs a DC voltage proportional to the peak value, and 8 is an oscilloscope that displays the waveform output from the peak detector 7'. FIG. 4 is a main block circuit diagram of the peak detector 7', in which 9 is an input circuit into which the pulse of the reflector amplified by the receiving circuit 6 is input, 10 is a trigger circuit, and 11 is a delay trigger pulse generator. 12 is a monitor circuit; 13 is a monitor synchro circuit; 14 is a delay trigger threshold setting circuit for setting a threshold to increase;
15 is a delay trigger circuit that sets the pulse width of a delay trigger that is activated when the level of the transmission pulse of the probe 4 exceeds the threshold; 15 is a delay circuit that sets the delay pulse width; 16 is a delay trigger circuit that sets the pulse width of the delay trigger; These gate circuits are capable of setting the gate pulse width to an arbitrary position and width, and are connected to the multiplexer 17 to form a gate control circuit 18 that adjusts the delay trigger, delay, and gate pulse widths. 19 is an RF that detects the pulse input to the input circuit 9;
A ridge wave circuit 20 converts the output signal of the RF detection circuit 19 into a DC'[pressure proportional to the value thereof and holds the value until the gate signal of the gate control circuit 18 is closed; 21 a peak detection circuit 20; This is an output circuit that outputs a DC voltage. FIG. 5 is a characteristic diagram illustrating a flaw detection method using the flaw detection device. In the figure, +8> is subject 3
This is an example of an echo pattern of a reflected wave from a transmission pulse, where T indicates a transmitted pulse, S indicates a surface echo, F indicates a defect echo, and B indicates a bottom echo. L is a line indicating the threshold level of the level of the transmission pulse T. fb) is the delay trigger circuit 14
(C) is the pulse width Pd of the communication trigger set in the delay circuit 15, (dl is the pulse width P9 of the gate set in the gate circuit 16).

探触子4から発射された送信パルスTのレベルが、設定
されたしきい値りを越すと直ち;こ遅延ト1)ガ回路1
4が作動し、遅延トリガのパルス・”、D pLが設定
される。続いて表面エコーSがしきい値りを越えると、
遅延回路15およびゲート回路16が作動してシーケン
スが始まり、遅延のパルス幅Pdが閉じると同時にゲー
トが開き、設定されたパルス幅P9経過後に閉じる。こ
こで第5図(d)に示すように、表面エコーSにおける
遅延のパルスが閉じると同時にゲートを開くように回路
を構成しても、回路間における信号の伝搬遅延時間P9
□が必ずあるから、あたかもゲートは遅延のパルス幅P
As soon as the level of the transmitted pulse T emitted from the probe 4 exceeds the set threshold;
4 is activated and the delay trigger pulse D pL is set.Subsequently, when the surface echo S exceeds the threshold,
The delay circuit 15 and gate circuit 16 operate to start the sequence, and the gate opens at the same time as the delay pulse width Pd closes, and closes after the set pulse width P9 has elapsed. Here, as shown in FIG. 5(d), even if the circuit is configured to open the gate at the same time as the delayed pulse in the surface echo S closes, the signal propagation delay time P9 between the circuits
Since there is always □, it is as if the gate has a delay pulse width P
.

が閉じてから伝搬遅延時間P 9n経過後に開いたと同
じ状態となり、パルス幅をP、に設定しても実際に開い
ているゲートのパルス幅はP9.となる。
After the propagation delay time P9n has elapsed after the gate is closed, it becomes the same state as if it were opened, and even if the pulse width is set to P, the pulse width of the actually open gate is P9. becomes.

そしてちょうど欠陥エコーFがパルス幅P、、内に含ま
れるようにされている。この状態は被検体3の厚さがあ
る程度例えば11前後の厚さ以上ある薄材の場合の探傷
において出現するが、被検体3の表面にきわめて近い微
細な表層欠陥や9.極薄材例えば厚さが200〜300
μm程度の被検体に内在する微細な欠陥を検査する場合
には、表面エコーSと欠陥エコーFがきわめて接近して
出現するため、欠陥エコーFを前記ゲートのパルス幅p
 9s内に出現させることができない。これは現在の遅
延回路15やゲート回路16で設定できる最小のパルス
幅Pa、P、、が約60〜80nsであり、この時間に
相当するパルスの伝搬距離が約350μmとなり、被検
体3の表面から欠陥部までの距離が約350μm以上で
なければ、欠陥エコーFはゲートのパルス幅P、内に出
現し得ないことを意味し、一方、前記表面から欠陥部ま
での距離が350μm以上であってパルス幅P9内に出
現しても、伝搬遅延時間P 911内に出現する程度の
被検体3の厚さや表層欠陥では事実上ゲートをかけたこ
とにならず、いずれも欠陥エコーFを検出することがで
きない、したがって被検体の検査をすることができない
不具合点があった。
The defective echo F is just included within the pulse width P, . This condition appears in flaw detection when the specimen 3 is a thin material with a certain thickness, for example around 11, or more, but it is caused by minute surface defects very close to the surface of the specimen 3. Ultra-thin material, e.g. thickness 200-300
When inspecting minute defects inherent in an object of about μm size, the surface echo S and the defect echo F appear very close to each other, so the defect echo F is divided into the pulse width p of the gate.
It cannot be made to appear within 9s. This is because the minimum pulse width Pa, P, which can be set with the current delay circuit 15 and gate circuit 16 is about 60 to 80 ns, and the propagation distance of the pulse corresponding to this time is about 350 μm, and the surface of the object 3 This means that unless the distance from the surface to the defect is about 350 μm or more, the defect echo F cannot appear within the gate pulse width P. On the other hand, if the distance from the surface to the defect is about 350 μm or more, Even if the defect echo F appears within the pulse width P9, if the thickness of the object 3 or the surface defect is such that it appears within the propagation delay time P911, it will not actually be gated, and the defect echo F will be detected in both cases. Therefore, there was a problem that it was impossible to test the subject.

〔発明の目的〕[Purpose of the invention]

本発明は前記従来技術の問題点を解消し、被検体の表面
にきわめて近い表層欠陥や極薄材に内在する微細な欠陥
を、回路間における信号の伝搬遅延時間に影響されるこ
となく、確実に欠陥エコーをゲートにかけて検査をする
ことができる超音波探傷方法を提供することを目的とす
る。
The present invention solves the above-mentioned problems of the prior art, and reliably detects surface defects very close to the surface of the test object and minute defects inherent in ultra-thin materials without being affected by the signal propagation delay time between circuits. The purpose of the present invention is to provide an ultrasonic flaw detection method that can perform inspection by gating defect echoes.

〔発明の概要〕[Summary of the invention]

本発明は探触子に超音波パルスを発信させるパルス回路
と、被検体の表面、欠陥および底面から反射する反射波
を前記探触子を介して受信し増幅する受信回路と、前記
探触子の送信パルスのレベルが、しきい値を越えたとき
に作動する遅延トリガのパルス幅を設定する遅延トリガ
回路やゲートのパルス幅を任意の位置と幅に設定できる
ゲート回路を有し、かつ前記受信回路で増幅された反射
波のピーク値を検波してその値に比例する電圧を出力す
るピークディテクタと、ピークディテクタから出力され
た波形を表示するオシロスコープとを備えた超音波探傷
装置により、液槽内の被検体を探傷する探傷方法におい
て、前記遅延トリガ回路により設定されたパルス幅が、
閉じられた後の最初に表れる前記被検体の表面から反射
する反射波の表面エコーのパルスで、前記ゲート回路を
作動させてゲートを開くようにすることにより、被検体
の表面にきわめて近い表層欠陥や極薄材に内在する微細
な欠陥を、回路間における信号の伝搬遅延時間に影響さ
れることなく、確実に欠陥エコーを検出して検査をする
ことができるようにした方法である。
The present invention includes a pulse circuit that causes a probe to emit ultrasonic pulses, a receiving circuit that receives and amplifies reflected waves reflected from the surface, defect, and bottom of an object through the probe, and a delay trigger circuit that sets the pulse width of a delay trigger that is activated when the level of the transmitted pulse exceeds a threshold; and a gate circuit that can set the pulse width of the gate to an arbitrary position and width; An ultrasonic flaw detection device equipped with a peak detector that detects the peak value of the reflected wave amplified by the receiving circuit and outputs a voltage proportional to that value, and an oscilloscope that displays the waveform output from the peak detector detects the peak value of the reflected wave amplified by the receiving circuit. In a flaw detection method for flaw detecting a test object in a tank, the pulse width set by the delay trigger circuit is
The pulse of the surface echo of the reflected wave reflected from the surface of the object that appears first after being closed activates the gate circuit to open the gate, thereby detecting a surface defect very close to the surface of the object. This method makes it possible to reliably detect defect echoes and inspect minute defects inherent in ultra-thin materials without being affected by signal propagation delay time between circuits.

〔発明の実施例〕[Embodiments of the invention]

本発明の1実施例を第1図および第2図により説明する
。第2図は本実施例のピークディチクタフの主要ブロッ
ク回路図で、前記従来の第4図に示すピークディテクタ
7′に比し遅延回路15を排した回路構成となっている
。第1図はピークディテクタ7を備えた前記第3図に示
す探傷装置を使用した探傷方法の説明用の特性線図であ
る。第1図および第2図において第3図ないし第5図と
同じ符号のものは同じものを示す。(a)のエコーパタ
ーンで示すように、被検体3の表面にきわめて近い表層
欠陥や極薄材に内在する微細な欠陥の欠陥エコーFは、
表面エコーSときわめて接近して出現する。このため本
発明では送信パルスTのレベルが、設定されたしきい値
りを越して遅延トリガ回路14が作動し、設定された山
)のパルス幅P、が閉じられると、表面エコーSのパル
スで遅延をかけずその後の最初に表れる前記表面エコー
Sのパルスで、ゲート回路16を作動させてゲートを開
くようにし、(d)のゲートのパルス幅P9内に表面エ
コーSと欠陥エコーFが含まれるようにする。この場合
ゲートのパルス幅2g内におけるエコーのピーク値は表
面エコーSとなるが、前記回路間における信号の伝搬遅
延時間P。があるからゲートのパルス幅はP9であって
も実際に開いているゲートのパルスI!ばP 9mとな
り、表面エコーSは伝搬遅延時間P9、内に入るため検
出されない。したがって結局パルス幅29m内における
欠陥エコーFのみが検出されそのピーク値を評価するこ
とができる。このように表面エコーSと欠陥エコーFと
が接近しているが分離して表示される表層欠陥や極薄材
の内部欠陥を、伝搬遅延時間のパルス幅P9、と表面エ
コーSの領域とを対応させるようシこして逆利用し確実
に検査することができる。
One embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 2 is a main block circuit diagram of the peak detector according to this embodiment, which has a circuit configuration in which the delay circuit 15 is eliminated compared to the conventional peak detector 7' shown in FIG. FIG. 1 is a characteristic diagram for explaining a flaw detection method using the flaw detection apparatus shown in FIG. 3, which is equipped with a peak detector 7. In FIGS. 1 and 2, the same reference numerals as in FIGS. 3 to 5 indicate the same components. As shown in the echo pattern in (a), the defect echo F of a surface defect very close to the surface of the object 3 or a minute defect inherent in an extremely thin material is
It appears very close to the surface echo S. Therefore, in the present invention, when the level of the transmission pulse T exceeds a set threshold value and the delay trigger circuit 14 is activated, and the pulse width P of the set peak is closed, the pulse of the surface echo S is The gate circuit 16 is activated to open the gate by the pulse of the surface echo S that appears first after that without delay, and the surface echo S and the defect echo F are generated within the pulse width P9 of the gate in (d). be included. In this case, the peak value of the echo within the gate pulse width 2g is the surface echo S, but the signal propagation delay time P between the circuits. Therefore, even if the gate pulse width is P9, the gate pulse I is actually open! In this case, P9m, and the surface echo S falls within the propagation delay time P9, so it is not detected. Therefore, in the end, only the defect echo F within the pulse width of 29 m is detected and its peak value can be evaluated. In this way, the surface echo S and the defect echo F are close to each other but are displayed separately, such as a surface defect or an internal defect of an ultra-thin material. It is possible to reliably inspect the information by reusing it in a corresponding manner.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、液槽内の被検体を探傷す
る探傷方法において、遅延トリガ回路により設定された
パルスの幅が、閉じられた後の最初に表れる前記被検体
の表面から反射する反射波の表面エコーのパルスで、ゲ
ート回路を作動させてゲートを開くようにしたから、被
検体の表面にきわめて近い表層欠陥や極薄材に内在する
微細な欠陥を、回路間の信号の伝搬遅延時間に影響され
ることなく、確実に欠陥エコーをゲートにかけて検出し
探傷することができる優れた効果を有する。
As explained above, the present invention provides a flaw detection method for detecting defects in a test object in a liquid tank, in which a pulse width set by a delay trigger circuit is reflected from the surface of the test object that first appears after closing. The pulse of the surface echo of the reflected wave activates the gate circuit and opens the gate, allowing the signal propagation between the circuits to detect surface defects very close to the surface of the object and minute defects inherent in ultra-thin materials. It has an excellent effect of being able to reliably gate and detect defect echoes and perform flaw detection without being affected by delay time.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の探傷方法の1例を説明する特性線図、
第2図は第1図に示す特性線図を出現するピークディテ
クタの主要ブロック回路の1例を示す図である。 第3図は一般的な探傷装置の構成説明図、第4図は従来
のピークディテクタの主要ブロック回路図、第5図は第
4図に示すピークディテクタを用いた従来の探傷方法を
説明する特性線図である。 l・・・水槽、3・・・被検体、4・・・探触子、5・
・・パルス回路、6・・・受信回路、7.7′・・・ピ
ークディテクタ、8・・・オシロスコープ、14・・・
遅延トリガ回路、15・・・遅延回路、16・・・ゲー
ト回路、S・・・表面エコー、F・・・欠陥エコー、P
 9n・・・伝搬遅延時間。 特許出願人  日立建機株式会社 株式会社 日立製作所 代理人 弁理士      秋 本 正 実第    
1    図 第2図 第 4 図 第5図 手続補正書(自発) 昭和61年5月12日
FIG. 1 is a characteristic diagram illustrating an example of the flaw detection method of the present invention;
FIG. 2 is a diagram showing an example of a main block circuit of a peak detector that appears in the characteristic diagram shown in FIG. 1. Fig. 3 is an explanatory diagram of the configuration of a general flaw detection device, Fig. 4 is a main block circuit diagram of a conventional peak detector, and Fig. 5 is a characteristic explaining the conventional flaw detection method using the peak detector shown in Fig. 4. It is a line diagram. l... Water tank, 3... Subject, 4... Probe, 5...
...Pulse circuit, 6...Reception circuit, 7.7'...Peak detector, 8...Oscilloscope, 14...
Delay trigger circuit, 15... Delay circuit, 16... Gate circuit, S... Surface echo, F... Defect echo, P
9n...Propagation delay time. Patent applicant Hitachi Construction Machinery Co., Ltd. Hitachi, Ltd. Agent Patent attorney Masaaki Akimoto
1 Figure 2 Figure 4 Procedural amendment to Figure 5 (voluntary) May 12, 1985

Claims (1)

【特許請求の範囲】 1、探触子に超音波パルスを発信させるパルス回路と、
被検体の表面、欠陥および底面から反射する反射波を前
記探触子を介して受信し増幅する受信回路と、前記探触
子の送信パルスのレベルが、しきい値を越えたときに作
動する遅延トリガのパルス幅を設定する遅延トリガ回路
やゲートのパルス幅を任意の位置と幅に設定できるゲー
ト回路を有し、かつ前記受信回路で増幅された反射波の
ピーク値を検波してその値に比例する電圧を出力するピ
ークディテクタと、ピークディテクタから出力された波
形を表示するオシロスコープとを備えた超音波探傷装置
により、液槽内の被検体を探傷する探傷方法において、
前記遅延トリガ回路により設定されたパルス幅が、閉じ
られた後の最初に表れる前記被検体の表面から反射する
反射波の表面エコーのパルスで、前記ゲート回路を作動
させてゲートを開くようにしたことを特徴とする超音波
探傷方法。 2、ゲート回路のゲートのパルス幅が、前記被検体の表
面エコーおよび欠陥エコーを含み、かつ前記超音波探傷
装置における回路間の信号の伝搬遅延時間を、前記表面
エコーの領域に対応させるようにしたことを特徴とする
特許請求の範囲第1項記載の超音波探傷方法。
[Claims] 1. A pulse circuit that causes a probe to emit ultrasonic pulses;
a receiving circuit that receives and amplifies reflected waves reflected from the surface, defect, and bottom surface of the object through the probe; and a receiving circuit that operates when the level of the transmitted pulse of the probe exceeds a threshold value. It has a delay trigger circuit that sets the pulse width of the delay trigger and a gate circuit that can set the pulse width of the gate to any position and width, and detects the peak value of the reflected wave amplified by the receiving circuit. In a flaw detection method that detects a specimen in a liquid tank using an ultrasonic flaw detection device equipped with a peak detector that outputs a voltage proportional to , and an oscilloscope that displays the waveform output from the peak detector,
The pulse width set by the delay trigger circuit activates the gate circuit to open the gate with a pulse of a surface echo of a reflected wave reflected from the surface of the subject that appears first after the gate is closed. An ultrasonic flaw detection method characterized by: 2. The pulse width of the gate of the gate circuit includes the surface echo and defect echo of the object to be inspected, and the propagation delay time of the signal between the circuits in the ultrasonic flaw detection device is made to correspond to the region of the surface echo. An ultrasonic flaw detection method according to claim 1, characterized in that:
JP60227007A 1985-10-14 1985-10-14 Method for ultrasonic flaw detection Pending JPS6287854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60227007A JPS6287854A (en) 1985-10-14 1985-10-14 Method for ultrasonic flaw detection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60227007A JPS6287854A (en) 1985-10-14 1985-10-14 Method for ultrasonic flaw detection

Publications (1)

Publication Number Publication Date
JPS6287854A true JPS6287854A (en) 1987-04-22

Family

ID=16854046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60227007A Pending JPS6287854A (en) 1985-10-14 1985-10-14 Method for ultrasonic flaw detection

Country Status (1)

Country Link
JP (1) JPS6287854A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291786A (en) * 1991-12-18 1994-03-08 Olympus Optical Co., Ltd. Ultrasonic microscope

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291786A (en) * 1991-12-18 1994-03-08 Olympus Optical Co., Ltd. Ultrasonic microscope

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