JPH0569382B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an ultrasonic flaw detection device for inspecting internal defects in materials or products, and particularly for testing near the surface of objects to be inspected, such as metal materials, ceramics, ICs, etc., and ultra-thin materials. This is a flaw detection device suitable for inspecting minute defects inherent in.

[Conventional technology]

In materials and industrial products, it has been conventional to detect internal defects in so-called thin materials, as well as defects that exist near the surface of the specimen even if the thickness is not so thin (hereinafter referred to as surface defects). It has been widely implemented in various technical fields. In order for the above-mentioned flaw detection to demonstrate much higher performance and functionality than conventional methods for new materials and electronic products, it is required to reliably detect surface defects and minute defects even closer to the surface. ing. A conventional general flaw detection device will be explained with reference to FIGS. 10 to 12. Figure 10 is an explanatory diagram of the configuration of the flaw detection device, in which 1 is a water tank filled with water 2, 3 is a thin material to be tested installed at the bottom of the water tank 1, and 4 is a probe immersed in water 2. be. 5 is a pulse transmitting circuit that periodically applies a pulse signal to the probe 4; 6 is a receiving circuit that receives and amplifies reflected waves reflected from the surface, defects, and bottom surface of the object 3 via the probe 4; 7′
8 is a peak detector that detects the peak value of the reflected wave amplified by the receiving circuit 6 and outputs a DC voltage proportional to that value, and 8 is an oscilloscope that displays the waveform output from the peak detector 7'.
FIG. 11 is a main block circuit diagram of the peak detector 7', in which the received signal received by the probe 4 is amplified by the receiving circuit 6 and then input to the input circuit 9 in the peak detector 7'. At the same time, the signal is input to the trigger circuit 10 in the gate control circuit 18 forming the peak detector 7'. This trigger circuit 10 outputs an ON signal when the signal level from the receiving circuit 6 exceeds a predetermined threshold.

On the other hand, the pulse signal from the pulse transmitting circuit 5 is transmitted to the delay trigger circuit 1 in the gate control circuit 18.
4, a delayed trigger signal with a predetermined pulse width is outputted to the delay circuit 15. At this time, the threshold value for the signal from the pulse generating circuit 5 that is input to the delay trigger circuit 14 is set by the delay trigger threshold setting circuit 11. Delay circuit 15
In this case, the signal from the trigger circuit 10 described above is first output after the input delayed trigger signal turns OFF.
When turned ON, a delayed pulse signal with a predetermined pulse width is output to the gate circuit 16 via the multivibrator 17a. The gate circuit 16 inputs the delayed pulse signal, and simultaneously outputs a gate signal with a predetermined pulse width to the input circuit 9 via the multivibrator 17b when the delayed pulse signal turns OFF.

The input circuit 9 outputs the signal from the receiving circuit 6 as it is to the RF detection circuit 19 only while the gate signal is ON. This RF detection circuit 19 outputs the integral value of the signal from the input circuit 9 to the peak detection circuit 20. In the peak detection circuit 20, the RF detection circuit 19
A DC voltage signal corresponding to the maximum value of the signal output from the oscilloscope 8 is held and output to an external oscilloscope 8.

The monitor circuit 12 is a buffer that outputs the above-mentioned gate signal to the oscilloscope 8, and the monitor synchronizer circuit 13 is a buffer that outputs a delayed trigger signal from the oscilloscope 8 as a synchronization signal of the output signal from the peak detector 7'. It is a batuaa for doing.

FIG. 12 is a chart showing the relationship among the received signal of the new probe 4, the delayed trigger signal in the peak detector 7', the delayed pulse signal, and the gate signal. In the figure, a indicates the received signal of the probe 4, T is the pulse wave generated immediately after the pulse signal is applied to the probe 4 from the pulse transmitting circuit 5, S is the surface echo, and F is the defective echo from the defective part. , B show bottom echoes from the bottom of the subject 3, respectively.
b is the delayed trigger signal from the delay trigger circuit 14, c is the delayed pulse signal from the delay circuit 15,
d indicates a gate signal from the gate circuit 16, respectively.

As described above, when the pulse signal is output from the pulse generation circuit 5, the delay trigger signal with the pulse width Pt is output from the delay trigger circuit 14. Then, after the delayed trigger signal is turned off, when a signal exceeding the threshold L, that is, a surface echo S is received for the first time, a delayed pulse signal with a pulse width Pd is output from the delay circuit 15. Then, at the same time that the delayed pulse signal turns OFF, a gate signal with a pulse width Pg is output from the gate circuit 16.

By the way, the minimum pulse widths P _d and P _g that can be set in the delay circuit 15 and gate circuit 16 that can be generated by the multivibrator 17 are about 60 ns to 80 ns, and the distance from the surface of the object 3 to its internal defect is For example, the defect echo F cannot appear within the gate pulse width P g unless it is approximately 350 μm or larger, and therefore, the defect echo F cannot appear within the pulse width P _g of the gate. For example, minute defects inherent in a material to be inspected with a thickness of about 200 μm to 300 μm cannot be detected and cannot be inspected. Furthermore, even when multiple defects exist close to each other in the thickness direction of the object, it is not possible to correctly gate only the defect echoes at a desired arbitrary depth, and it is difficult to accurately gate only the defect echoes at a desired depth. There was a problem that it was not possible to perform flaw detection.

[Problem that the invention seeks to solve]

As mentioned above, in conventional ultrasonic flaw detection equipment, the minimum pulse width that can be set in the delay circuit and gate circuit is long, approximately 60 ns to 80 ns. Since it was not possible to detect and gate only the defect echoes at a desired arbitrary depth, it was not possible to detect each defect when there were multiple defects close to each other in the thickness direction. It had some problems.

The present invention solves the above-mentioned problems of the prior art, and makes it possible to detect defects in the ultra-thin specimen and the surface layer, and to detect multiple defects that are close to each other in the thickness direction. An object of the present invention is to provide an ultrasonic flaw detection device that can detect any flaws, even if they exist.

[Means for solving problems]

The present invention provides a probe that is placed opposite to a subject in a liquid bath and transmits and receives ultrasonic waves, a pulse transmission circuit that periodically applies pulse signals to the probe, and ultrasonic waves that are received by the probe. provided in an ultrasonic flaw detection apparatus having a receiving circuit for amplifying a sound wave signal, inputting the pulse signal from the pulse oscillation circuit and the amplified signal from the receiving circuit, and detecting the signal from the receiving circuit based on these signals. In order to output a DC voltage proportional to the detected peak value, a delay trigger circuit outputs a delayed totoga signal having a predetermined pulse width after inputting the pulse signal from the pulse generating circuit, and the delayed trigger signal is turned OFF. a delay circuit that outputs a delayed pulse signal having a predetermined pulse width when a signal of a predetermined value or more is input from the receiving circuit at the time; a gate circuit that outputs a gate signal having a pulse width of; inputting the signal from the receiving circuit and the gate signal; detecting the signal from the receiving circuit according to the gate signal; In the gate setting circuit for a peak detector, the gate setting circuit for a peak detector is provided with a peak detection means for outputting a peak detector, which inputs the delayed pulse signal, delays the delayed pulse signal by a predetermined period of time, and further integrates the delayed signal with the delayed pulse signal. a first delay logic circuit that outputs a logical product to the gate circuit; a first delay logic circuit that receives the gate signal, delays the gate signal for a predetermined period of time, and outputs a logical product of the delayed signal and the gate signal to the peak circuit; This configuration includes a second delay logic circuit that outputs to the detection means.

The first delay logic circuit includes a delay circuit that receives the delayed pulse signal and delays the delayed pulse signal for a predetermined period of time, an inverting circuit that inverts the signal from the delay circuit, and a delay circuit that inverts the signal from the delay circuit. and an AND circuit that inputs the signal and the delayed pulse signal and calculates and outputs the logical product of both signals.Meanwhile, the second delay logic circuit inputs the gate signal and outputs the gate signal. A delay circuit that delays a predetermined period of time, an inversion circuit that inverts the signal from the delay circuit, and an AND circuit that inputs the signal from the inversion circuit and the gate signal, and calculates and outputs the AND of both signals. Preferably, the configuration is configured.

Further, the first delay logic circuit includes a pulse delay circuit which inputs the delayed pulse signal and has a predetermined number of inverters and buffers connected in series to delay the delayed pulse signal by a predetermined time; and an AND circuit that inputs the signal from the gate signal and the delayed pulse signal and calculates and outputs the logical product of both signals, while the second delay logic circuit inputs the gate signal and outputs the logical product of both signals. A pulse delay circuit including a predetermined number of inverters and buffers connected in series in order to delay a signal for a predetermined time, a signal from this pulse delay circuit and the gate signal are input, and the logical product of both signals is calculated and output. It is desirable that the circuit be constructed from an AND circuit.

[Effect]

The present invention has the above configuration, and when a pulse signal from the pulse generating circuit is input to the delay trigger circuit, a delay trigger signal having a predetermined pulse width is output to the delay circuit. When the delay circuit receives a signal of a predetermined value or more from the receiving circuit after the delay trigger signal is turned off, a delay pulse signal having a predetermined pulse width is output to the first delay logic circuit. In this first delay logic circuit,
The logical product of the delayed pulse signal and a signal obtained by delaying the delayed pulse signal by a predetermined time is output to the gate circuit. The gate circuit outputs a gate signal having a predetermined pulse width to the second delay logic circuit at the same time as the signal from the first delay logic circuit turns OFF. This second delay logic circuit outputs the logical product of the gate signal and a signal obtained by delaying the gate signal by a predetermined time to the peak detection means.

As described above, in the present invention, when a pulse signal is output from the pulse transmitting circuit and a time corresponding to the panel width of the delayed trigger signal has elapsed, when a signal equal to or higher than the threshold value is input from the receiving circuit, at this point A signal corresponding to the delay time from when the delayed pulse signal is delayed for a predetermined time by the first delay logic circuit is input to the gate circuit. And this signal
A signal corresponding to the delay time from when the gate signal is turned off to when the gate signal is delayed for a predetermined time by the second delay logic circuit is outputted to the peak detection means as a new gate signal. This allows the first
By setting the delay time in the first delay logic circuit and the delay time in the second delay logic circuit, the gate signal is
The ON time or the timing of the rise of the gate signal can be adjusted as desired.

Therefore, even surface defects present on the surface of the object can be accurately detected.

〔Example〕

Embodiments of the present invention will be described with reference to FIGS. 1 to 4. In the figures, the same reference numerals as in FIGS. 10 to 12 indicate the same things. Figures 1 to 4 are explanatory diagrams of the first embodiment, where Figure 1 is a main block circuit diagram of the peak detector, Figure 2 is a detailed block circuit diagram of the main part of Figure 1, and Figure 3 is a detailed block circuit diagram of the main part of Figure 1. 4 is a characteristic diagram thereof, and FIG. 4 is an echo pattern when a plurality of defects are present close to each other in the thickness direction of the object. In this first embodiment, the peak detector 7' according to the prior art shown in FIG. It has a delay logic circuit 25a and a delay logic circuit 25b which calculates and outputs the AND of the gate signal from the gate circuit 16 and a signal obtained by delaying the gate signal by a predetermined time.

The delay logic circuit 25a is a delay circuit that delays a delay pulse signal inputted through the multivibrator 17a for a predetermined time, such as a delay element 2.
2a, an inversion circuit 23a that inverts and outputs the signal from the delay element 22a, and a logic circuit 24a that calculates and outputs the AND of the delayed pulse signal and the output signal from the inversion circuit 23a. On the other hand, the delay logic circuit 25b includes a delay circuit that delays a gate signal input via the multivibrator 17b for a predetermined period of time, such as a delay element 22b, and an inversion circuit 23b that inverts and outputs the signal from this delay element 22b. , and a logic circuit 24b that calculates and outputs the AND of the delayed pulse signal and the output signal from the inversion circuit 23b.

If the defect inherent in the object is a surface defect, or if the object is an extremely thin material and contains a defect, the defect echo F will appear very close to the surface echo S, and the echo pattern will be An example is shown in a of FIG. As soon as the pulse signal from the pulse generator circuit exceeds the threshold value L, the delay trigger circuit 14 is activated and the pulse width is increased as shown in b.
The delayed trigger signal of Pt is output to the delay circuit 15,
When the surface echo S exceeds the threshold value L after the delayed trigger signal is turned off, a delayed pulse signal with a pulse width Pd is outputted to the delay logic circuit 25a via the multivibrator 17a, as shown in c.
Then, the delay element 22a forming the delay logic circuit 25a delays the input delay pulse signal by a preset time P'd as shown in d, and sends the input delay pulse signal to the inverting circuit 25a.
Output to 3a. The inverting circuit 23a inverts the delayed pulse signal delayed by P'd as shown in e,
It is output to the AND circuit 24a. AND circuit 24a
outputs the AND of the delayed pulse signal input directly from the multivibrator 17a and the signal from the inversion circuit 23a. The signal from the AND circuit 24a rises immediately after the surface echo S is received, as shown in f, and has a pulse width corresponding to the delay time P'd set in the delay element 22a.

This signal is then input to the gate circuit 16, and at the same time as this signal is turned OFF, a gate signal with a pulse width Pg is outputted from the gate circuit 16 as shown in g. This gate signal is input to the delay logic circuit 25b via the multivibrator 17b. . The delay element 22b forming the delay logic circuit 25b delays the input gate signal by a preset time P'g and outputs the delayed signal to the inversion circuit 23b, as shown in h. The inverting circuit 23b inverts the gate signal delayed by P'g as shown in i, and outputs it to the AND circuit 24b. AND circuit 2
4b outputs the AND of the gate signal directly input from the multivibrator 17b and the signal from the inverting circuit 23b. The signal from the AND circuit 24b becomes a signal having a pulse width corresponding to the delay time P'g set in the delay element 22b, as shown in j.

Since the delay elements 22a and 22b can set their respective delay times arbitrarily, the pulse width of the signals output from the AND circuits 24a and 24b is
P′d and P′g can also be adjusted arbitrarily accordingly. In other words, since the delay time P'g is set corresponding to the time width in which the defective echo F appears,
The AND pulse of j can be arbitrarily set corresponding to the time width of the defective echo F. This is true, for example, when the echo pattern shows that multiple defective echoes F ₁ , F ₂ , and F ₃ are located close to each other in the thickness direction of the object, as shown in FIG. This shows that it is possible to arbitrarily apply gates to each defect echo or any defective echo, making it possible to detect multiple defects that exist in close proximity.

5 to 9 are explanatory diagrams of the second embodiment, in which FIG. 5 is a detailed block circuit diagram of the main part of the peak detector, FIG. 6 is its characteristic diagram, and FIG. 7 is the diagram shown in FIG. Figure 7a is a block diagram showing the configuration of the pulse delay circuit.
Figure b is a pulse propagation characteristic diagram. Figure 8 is the 5th
An explanatory diagram of another example of the pulse delay circuit in the figure.
FIG. 8a is a block diagram of the configuration, FIG. 8b is a pulse propagation characteristic diagram, FIG. 9 is an explanatory diagram of another example of FIG. 8, and FIG. 9a is a block diagram of the configuration. b is a pulse propagation characteristic diagram. In this embodiment, the first
This embodiment is the same except that the configurations of the delay logic circuits 25a and 25b are different. Delay logic circuit 2
8a is a pulse delay circuit 26a which is composed of an inverter or a buffer of logic elements that delays the delayed pulse signal input from the delay circuit 15 via the multivibrator 17a by an arbitrary time; and an output pulse of the pulse delay circuit 26a. It is composed of an AND circuit 27a that outputs an AND with the output pulse of the multivibrator 17a, and one delay logic circuit 28b has the same structure as the delay logic circuit 28a.

FIG. 6 a shows an echo pattern similar to the echo pattern in which the defect echo F and the surface echo S appear very close to each other as shown in FIG. 3 a. When the surface echo S exceeds the threshold L after the ultrasonic wave is emitted from the probe and the delayed trigger signal b turns OFF, the delay circuit 15 generates a delayed pulse signal with a pulse width Pd as shown in c. is output to the delay logic circuit 28a via the multivibrator 17a. The pulse delay circuit 26a is composed of an inverter 29 and a buffer 30, for example, as shown in FIG. 7a, and its switching characteristics cause a propagation delay time of the output pulse with respect to the input pulse, and usually one stage is delayed by about 10 ns. Assuming that the inlet of the pulse delay circuit 26a is the x end, the connection point between the inverter 29 and the buffer 30 is the y end, and the exit of the pulse delay circuit 26a is the z end, the y end is about It is propagated with a delay of 10ns, and approximately
It has the characteristic of propagating with a 10ns delay. The pulse that has passed through the pulse delay circuit 26a having such characteristics has a pulse delay of d in FIG. 6. This d
The AND circuit 2 combines the pulse delay of and the delayed pulse of c.
7a, and the AND of both pulses is taken. The AND pulse of e obtained by ANDing is sent to the pulse delay circuit 26.
The time P′ _d delayed by a (approximately 20 ns in the example of Fig. 7 b)
The pulse width is the same as that of the pulse width, and is output from the delay logic circuit 28a. The output logical product pulse of e is
Gate circuit 16 via multivibrator 17b
is output to.

On the other hand, the signal input to the gate circuit 16 is
At the same time as turning off, the gate circuit 16 outputs a pulse signal with a pulse width Pg to the delay logic circuit 28b via the multivibrator 17b, as shown in f. The pulse delay circuit 26b has the same configuration and propagation characteristics as the pulse delay circuit 26a,
The pulse that has passed through the pulse delay circuit 26b has a pulse delay of g in FIG. This pulse delay of g and the gate pulse of f are input to the AND circuit 27b, and the AND of both pulses is calculated. The ANDed pulse of h has the same pulse width as the time P′ _g delayed by the pulse delay circuit 26b (approximately 20 ns in the example of FIG. 7b), and is output from the delay logic circuit 28b. .

The AND pulses e and h can be generated by adopting various configurations that change the combination of the inverter 29 and the buffer 30 and the number of connected stages, in addition to the configuration of the pulse delay circuits 26a and 26b shown in FIG. It can be set at any position and with any pulse width. For example, FIG. 8a shows a case where four stages of inverters 29 are connected to the pulse delay circuits 26a and 26b, and the delay time in that case is
As shown in Figure b, the pulse input to the x end is delayed by approximately 10 ns x 4 = 40 ns at the z end. In addition, Fig. 9a shows a configuration in which 4 stages of inverters 29 and 1 stage of buffer 30 are connected, totaling 5 stages.
As shown in Figure b, approximately 10ns x 5 for the input at the x end.
=50ns delay will occur at the z end. Therefore, by outputting the input pulse from any number of stages, the delay time can be set arbitrarily, and the pulse width of the AND pulse of e and h can be set arbitrarily. Even when there are multiple defects close to each other in the thickness direction of the object as shown in the echo pattern shown in Figure 4, gates can be set arbitrarily for each defect or for a defect at a desired depth. can be applied.

As can be seen from the above configuration, there is no problem even if the delayed pulse c shown in FIGS. 3 and 6 is set to a pulse width that includes the defective echo F.

〔Effect of the invention〕

As explained above, the present invention inputs a delayed pulse signal to the gate setting circuit of a peak detector, delays this delayed pulse signal for a predetermined time, and
Furthermore, a first delay logic circuit outputs the logical product of the delayed signal and the delayed pulse signal to the gate circuit; Since the configuration includes a second delay logic circuit that outputs the AND of the gate signal and the gate signal to the peak detection means, it is possible to detect defects in ultra-thin materials and surface defects, and Even if there are multiple defects that are close to each other in the thickness direction, gates can be applied to the desired defects to be detected, making it possible to perform accurate flaw detection, which has excellent practical effects. .

[Brief explanation of the drawing]

FIG. 1 is a main block circuit diagram of a peak detector according to a first embodiment of the present invention, FIG. 2 is a detailed block circuit diagram of the main part of FIG. 1, and FIG. 3 is a characteristic diagram of FIG. 1. FIG. 4 shows an example of an echo pattern when a plurality of defects exist close to each other in the thickness direction of the object, and FIG. 5 shows an example of an echo pattern of a peak detector according to a second embodiment of the present invention. A detailed block circuit diagram of the main parts, FIG. 6 is a characteristic diagram of FIG. 5, FIG. 7 is a diagram showing an example of the pulse delay circuit of FIG. 5, and FIG. 7a is a block diagram showing the configuration. 7b is a pulse propagation characteristic diagram, FIG. 8 is a diagram showing another example of the pulse delay circuit of FIG. 5, FIG. 8a is a configuration block diagram, and FIG.
FIG. 9b is a pulse propagation characteristic diagram, FIG. 9 is a diagram showing another example of FIG. 8, FIG. 9a is a block diagram, and FIG. 9b is a pulse propagation characteristic diagram. Fig. 10 is an explanatory diagram of the configuration of an ultrasonic flaw detection device, Fig. 11 is a main block circuit diagram of a conventional peak detector, and Fig. 12 is an explanatory diagram of the configuration of an ultrasonic flaw detection device.
The figure is a characteristic diagram of FIG. 11.

Claims (1)

[Scope of Claims] 1. A probe that is placed opposite to a subject in a liquid tank and transmits and receives ultrasonic waves; A pulse generating circuit that periodically applies pulse signals to the probe; provided in an ultrasonic flaw detection apparatus having a receiving circuit that amplifies a received ultrasonic signal, inputs a pulse signal from the pulse transmitting circuit and an amplified signal from the receiving circuit, and receives an amplified signal from the receiving circuit based on these signals. a delay trigger circuit that outputs a delayed trigger signal having a predetermined pulse width after inputting the pulse signal from the pulse generating circuit in order to detect the signal and output a DC voltage proportional to the peak value; a delay circuit that outputs a delayed pulse signal having a predetermined pulse width when a signal of a predetermined value or more is input from the receiving circuit when the signal is OFF; a gate circuit that outputs a gate signal having a predetermined pulse width at the same time that A gate setting circuit for a peak detector is provided with a peak detection means for outputting a DC voltage signal, which inputs the delayed pulse signal, delays the delayed pulse signal by a predetermined time, and further combines the delayed signal with the delayed signal. a first delay logic circuit that outputs an AND with a pulse signal to the gate circuit; a first delay logic circuit that receives the gate signal and delays the gate signal for a predetermined time; A gate setting circuit for a peak detector, comprising: a second delay logic circuit that outputs the product to the peak detection means. 2. The first delay logic circuit includes a delay circuit that inputs the delayed pulse signal and delays the delayed pulse signal by a predetermined time, an inverting circuit that inverts the signal from the delay circuit, and a signal from the inverting circuit. and an AND circuit that inputs the delayed pulse signal and calculates and outputs the logical product of both signals, and further, the second delay logic circuit inputs the gate signal and outputs the logical product of both signals for a predetermined period of time. It consists of a delay circuit that delays, an inversion circuit that inverts the signal from this delay circuit, and an AND circuit that inputs the signal from this inversion circuit and the gate signal, and calculates and outputs the AND of both signals. 2. A gate setting circuit for a peak detector according to claim 1. 3. The first delay logic circuit includes a pulse delay circuit in which a predetermined number of inverters and buffers are connected in series to input the delayed pulse signal and delay the delayed pulse signal for a predetermined time; and an AND circuit that inputs the signal and the delayed pulse signal and calculates and outputs the logical product of both signals, and further, the second delay logic circuit inputs the gate signal and outputs the logical product of the gate signal. a pulse delay circuit in which a predetermined number of inverter buffers are connected in series in order to delay the output for a predetermined time; and an AND circuit that inputs the signal from this pulse delay circuit and the gate signal, and calculates and outputs the AND of both signals. 2. The gate setting circuit for a peak detector according to claim 1, further comprising a gate setting circuit for a peak detector.