JPS6364950B2 - - Google Patents

Info

Publication number
JPS6364950B2
JPS6364950B2 JP951580A JP951580A JPS6364950B2 JP S6364950 B2 JPS6364950 B2 JP S6364950B2 JP 951580 A JP951580 A JP 951580A JP 951580 A JP951580 A JP 951580A JP S6364950 B2 JPS6364950 B2 JP S6364950B2
Authority
JP
Japan
Prior art keywords
potential
cathode
capacitor
ray tube
cathode ray
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP951580A
Other languages
Japanese (ja)
Other versions
JPS56106473A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP951580A priority Critical patent/JPS56106473A/en
Publication of JPS56106473A publication Critical patent/JPS56106473A/en
Publication of JPS6364950B2 publication Critical patent/JPS6364950B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/20Prevention of damage to cathode-ray tubes in the event of failure of scanning

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Details Of Television Scanning (AREA)

Description

【発明の詳細な説明】 本発明は画像表示装置の輝点消去回路に係り、
特に映像増幅段とブラウン管のカソード又はグリ
ツド電極とを直流結合した場合に従来生じていた
輝点を消去する同回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bright spot erasing circuit for an image display device,
In particular, the present invention relates to a circuit for eliminating bright spots that conventionally occur when a video amplification stage and a cathode or grid electrode of a cathode ray tube are coupled with direct current.

次に本発明について図面を用いて説明すると、
第1図は本発明回路、第2図イ、ロ、ハは同回路
の説明波形図であり、1はB電圧印加端子、2は
映像信号印加端子、3は結合用コンデンサ、4は
コントラスト調整用の可変抵抗器、5は直流再生
回路、6は分圧抵抗7,8を有する分圧回路、9
は出力トランジスタ10,11を有する映像増幅
段、12はピーキングコイル、13は負荷抵抗、
14,15は前記出力トランジスタのコレクタに
対して直列に順方向接続した第1及び第2ダイオ
ード、16はデカツプリングコンデンサ、17は
第1コンデンサ、18は第2コンデンサ19及び
抵抗20を有する時定数回路、21は輝度調整用
の可変抵抗器、22,23はブラウン管24のヒ
ータ25に電圧を印加するヒータ電圧印加端子を
示す。
Next, the present invention will be explained using drawings.
Figure 1 is the circuit of the present invention, Figure 2 A, B, and C are explanatory waveform diagrams of the same circuit, where 1 is the B voltage application terminal, 2 is the video signal application terminal, 3 is the coupling capacitor, and 4 is the contrast adjustment. 5 is a DC regeneration circuit, 6 is a voltage dividing circuit having voltage dividing resistors 7 and 8, 9 is a variable resistor for
is a video amplification stage having output transistors 10 and 11, 12 is a peaking coil, 13 is a load resistance,
14 and 15 are first and second diodes connected in series in a forward direction to the collector of the output transistor, 16 is a decoupling capacitor, 17 is a first capacitor, and 18 is a second capacitor 19 and a resistor 20. A constant circuit, 21 is a variable resistor for brightness adjustment, and 22 and 23 are heater voltage application terminals for applying voltage to the heater 25 of the cathode ray tube 24.

次に本発明の動作について説明すると、映像信
号は端子2に加えられ、出力トランジスタ11は
エミツタ接地、出力トランジスタ10はベース接
地で動作し、出力トランジスタ10のベースは、
分圧抵抗7,8にて所定のバイアス電圧が与えら
れている。
Next, to explain the operation of the present invention, a video signal is applied to the terminal 2, the output transistor 11 operates with its emitter grounded, and the output transistor 10 operates with its base grounded, and the base of the output transistor 10 is
A predetermined bias voltage is applied by voltage dividing resistors 7 and 8.

このときブラウン管24のカソードには、前記
直流再生回路5にて直流分再生が行われた状態
で、映像信号が加わり、前記出力トランジスタ1
0のコレクタ電極には、水平偏向回路(図示せ
ず)から導出されたフライバツクパルス(FBP)
がダイオード14,15及び負荷抵抗13とピー
キングコイル12を介して(その際、前記ダイオ
ード14及び第1コンデンサ17にて整流され
て)、直流電圧となつて加わつている。前記ブラ
ウン管24のグリツドには輝度調整用の可変抵抗
器21によつて所定のバイアス電圧(負電圧)が
加えられている。
At this time, a video signal is applied to the cathode of the cathode ray tube 24 with the DC component being regenerated by the DC regeneration circuit 5, and the output transistor 1
The collector electrode of 0 has a flyback pulse (FBP) derived from a horizontal deflection circuit (not shown).
is applied as a DC voltage via the diodes 14 and 15, the load resistor 13, and the peaking coil 12 (at this time, it is rectified by the diode 14 and the first capacitor 17). A predetermined bias voltage (negative voltage) is applied to the grid of the cathode ray tube 24 by a variable resistor 21 for brightness adjustment.

従つて通常動作時出力トランジスタ10のB電
圧としての+B1はダイオード14及び第1コン
デンサ17で整流、平滑されて前記トランジスタ
10の負荷抵抗13の一端に供給され、同時にダ
イオード15は導通状態であり、第2コンデンサ
20は抵抗19を介して充電された状態となつて
いる。
Therefore, during normal operation, + B1 as the B voltage of the output transistor 10 is rectified and smoothed by the diode 14 and the first capacitor 17, and is supplied to one end of the load resistor 13 of the transistor 10, and at the same time, the diode 15 is in a conductive state. , the second capacitor 20 is in a charged state via the resistor 19.

前記結合コンデンサ3も図示の極性で充電され
た状態となつている。
The coupling capacitor 3 is also charged with the polarity shown.

次に電源スイツチ(図示せず)をオフして切換
えたとき、前記結合コンデンサ3の電荷が放電す
ることによつて、出力トランジスタ10,11が
一瞬導通状態となり、前記電源スイツチのオフに
伴い、フライバツクパルス(FBP)はなくなり、
端子26はアース電位となつて第1ダイオード1
4はカツトオフとなる。第1コンデンサ17に蓄
積された電荷は第2ダイオード15及び出力トラ
ンジスタ10,11を通して放電し、該第1コン
デンサ17の電荷がなくなると、前記第2ダイオ
ード15のアノード側がアース電位になつてカツ
トオフになる。
Next, when the power switch (not shown) is turned off and switched, the charge in the coupling capacitor 3 is discharged, so that the output transistors 10 and 11 become conductive for a moment, and as the power switch is turned off, Flyback pulse (FBP) is gone;
The terminal 26 is at ground potential and the first diode 1
4 is the cutoff. The charge accumulated in the first capacitor 17 is discharged through the second diode 15 and the output transistors 10 and 11, and when the charge in the first capacitor 17 is exhausted, the anode side of the second diode 15 becomes the ground potential and is cut off. Become.

一方、抵抗19及び第2コンデンサ20より成
る時定数回路18が放電を開始するが、前記結合
コンデンサ3の電荷の放電後は、出力トランジス
タ10,11はカツトオフになることから、第2
ダイオード15はカツトオフになる。
On the other hand, the time constant circuit 18 consisting of the resistor 19 and the second capacitor 20 starts discharging, but since the output transistors 10 and 11 are cut off after the charge of the coupling capacitor 3 is discharged, the second
Diode 15 is cut off.

従つてブラウン管24のカソード電位VB1は、
前記第2コンデンサ20の充電された電位に保持
される。この電位を前記ブラウン管24のカツト
オフ以上の電位に設定してあるので、ブラウン管
のカソード電流は流れず、輝点(スポツト)が阻
止される。
Therefore, the cathode potential V B1 of the cathode ray tube 24 is
The second capacitor 20 is held at the charged potential. Since this potential is set at a potential higher than the cut-off potential of the cathode ray tube 24, no cathode current of the cathode ray tube flows and bright spots are prevented.

この模様を第2図を用いて説明すると、t0は電
源スイツチのオフのタイミング、t1はブラウン管
24のヒータ25が冷却するタイミング、Vk
前記カソード電位を示し、Vk0は前記ブラウン管
のカソードのカツトオフ電位を示し、第2図イは
前述の説明で、スイツチオフ後ブラウン管のヒー
タが冷却してからカソード電位VkがVk0に達し、
次第に減少する場合である。
To explain this pattern using FIG. 2, t 0 is the timing when the power switch is turned off, t 1 is the timing when the heater 25 of the cathode ray tube 24 cools down, V k is the cathode potential, and V k0 is the timing when the heater 25 of the cathode ray tube 24 cools down. Figure 2A shows the cut-off potential of the cathode, and as explained above, after the heater of the cathode ray tube cools down after the switch-off, the cathode potential V k reaches V k0 .
This is a case where it gradually decreases.

時定数回路18の時定数は、出力トランジスタ
10のコレクタ電位等によつても異なるが、第2
図ロの如くブラウン管24の第1グリツド電位が
ゼロとなつてもカツトオフ以上とならないときに
は略期間t0〜t0′に相当する時間に水平偏向回路が
動作している場合、即ちラスタが残つている状態
で、出力トランジスタのカツトオフ後、ブラウン
管24のカソード電位Vkは再び上昇即ち第2コ
ンデンサ20の電荷の放電が始まり、その後はリ
ークにより徐々に放電するので、ヒータ25の冷
却するまでは前記電位VkはVk0以上に保たれてい
るので、輝点(スポツト)が防止できる。
The time constant of the time constant circuit 18 varies depending on the collector potential of the output transistor 10, etc.
As shown in Figure B, when the first grid potential of the cathode ray tube 24 becomes zero but does not rise above the cutoff, the horizontal deflection circuit is operating during a period corresponding to approximately the period t 0 to t 0 ', that is, the raster remains. In this state, after the output transistor is cut off, the cathode potential V k of the cathode ray tube 24 rises again, that is, the charge in the second capacitor 20 begins to discharge, and then gradually discharges due to leakage. Since the potential V k is maintained above V k0 , bright spots can be prevented.

第2図ハは、前記第2コンデンサ20と抵抗に
よつて定まる時定数Tがヒータ25の冷却する迄
の時間より小なる場合で、t0″〜t1の間は輝点(ス
ポツト)が出てしまう。
FIG. 2C shows a case where the time constant T determined by the second capacitor 20 and the resistor is smaller than the time required for the heater 25 to cool down, and there is no bright spot between t0 '' and t1 . It comes out.

そこで本発明は前記時定数回路18の時定数T
を大にしてあり、一実施例としてR=22KΩ、C2
=22μFになし、又C0=1000μF、C1=10μFになす
と電源スイツチのオフ後、ブラウン管のカソード
電位がカツトオフ電位以下に達する迄の時間が約
3分になつて輝点は未然に阻止し得た。
Therefore, the present invention provides a time constant T of the time constant circuit 18 .
As an example, R=22KΩ, C 2
= 22μF, C 0 = 1000μF, and C 1 = 10μF, it takes about 3 minutes for the cathode potential of the cathode ray tube to reach the cut-off potential or less after the power switch is turned off, and bright spots are prevented. I was able to do it.

尚前記輝点消去のための時定数回路は、ブラウ
ン管のカソード側に接続した例について示した
が、ブラウン管のグリツド側に接続し、該ブラウ
ン管のグリツド電位を電源スイツチ後、ヒータが
冷却する迄カツトオフ以下に保てば、前述と同様
の効果が得られる。
The time constant circuit for eliminating bright spots is connected to the cathode side of the cathode ray tube in the example shown above, but it is connected to the grid side of the cathode ray tube, and the grid potential of the cathode ray tube is cut off after the power switch is turned on until the heater cools down. If it is maintained below, the same effect as described above can be obtained.

以上の通り本発明によれば、テレビ受像機、ビ
デオモニタ及びキヤラクタデイスプレイ等の画像
表示装置において、電源スイツチのオフ時に発生
していた輝点(スポツト)をダイオード及び時定
数回路にて容易に防止し得、本発明回路は同装置
にとつて効果大となる。
As described above, according to the present invention, in image display devices such as television receivers, video monitors, and character displays, bright spots that occur when the power switch is turned off can be easily eliminated using a diode and a time constant circuit. This can be prevented, and the circuit of the present invention is highly effective for the same device.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の輝点消去回路、第2図イ,
ロ,ハは第1図の説明波形図を示す。 主な図番の説明、9…映像増幅段、10,11
…出力トランジスタ、13…負荷抵抗、14…第
1ダイオード、15…第2ダイオード、17…第
1コンデンサ、18…時定数回路、20…第2コ
ンデンサ、24…ブラウン管。
Figure 1 shows the bright spot erasing circuit of the present invention, Figure 2 A,
B and C show explanatory waveform diagrams of FIG. Explanation of main drawing numbers, 9...Video amplification stage, 10, 11
...Output transistor, 13...Load resistor, 14...First diode, 15...Second diode, 17...First capacitor, 18 ...Time constant circuit, 20...Second capacitor, 24...Cathode ray tube.

Claims (1)

【特許請求の範囲】[Claims] 1 ブラウン管のカソード又はグリツド電極と映
像増幅段とが直流結合されている画像表示装置に
おいて、前記映像増幅段の出力トランジスタの出
力電極を前記カソード又はグリツド電極に直流結
合すると共に前記出力トランジスタの負荷とフラ
イバツクパルス印加端子との間に複数のダイオー
ドを直列接続して、前記複数のダイオード間の接
続点とアース間に第1コンデンサを接続し、前記
負荷とアース間に第2コンデンサを有する時定数
回路を接続することにより、電源オフ後、少なく
とも前記ヒータが冷却する迄、前記時定数回路に
よりカソード電位をカツトオフ電位以上若しくは
グリツド電位をカツトオフ電位以下に保持してな
る輝度消去回路。
1. In an image display device in which a cathode or grid electrode of a cathode ray tube and a video amplification stage are DC-coupled, the output electrode of an output transistor of the video amplification stage is DC-coupled to the cathode or grid electrode, and the load of the output transistor is A time constant having a plurality of diodes connected in series between the flyback pulse application terminal, a first capacitor connected between the connection point between the plurality of diodes and the ground, and a second capacitor between the load and the ground. By connecting a circuit, the time constant circuit maintains the cathode potential at or above the cut-off potential or the grid potential at or below the cut-off potential after the power is turned off, at least until the heater cools down.
JP951580A 1980-01-29 1980-01-29 Bright sopt erasing circuit Granted JPS56106473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP951580A JPS56106473A (en) 1980-01-29 1980-01-29 Bright sopt erasing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP951580A JPS56106473A (en) 1980-01-29 1980-01-29 Bright sopt erasing circuit

Publications (2)

Publication Number Publication Date
JPS56106473A JPS56106473A (en) 1981-08-24
JPS6364950B2 true JPS6364950B2 (en) 1988-12-14

Family

ID=11722387

Family Applications (1)

Application Number Title Priority Date Filing Date
JP951580A Granted JPS56106473A (en) 1980-01-29 1980-01-29 Bright sopt erasing circuit

Country Status (1)

Country Link
JP (1) JPS56106473A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134364U (en) * 1984-02-17 1985-09-06 株式会社富士通ゼネラル TV receiver spot killer device

Also Published As

Publication number Publication date
JPS56106473A (en) 1981-08-24

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