JPS6113429B2 - - Google Patents
Info
- Publication number
- JPS6113429B2 JPS6113429B2 JP17549481A JP17549481A JPS6113429B2 JP S6113429 B2 JPS6113429 B2 JP S6113429B2 JP 17549481 A JP17549481 A JP 17549481A JP 17549481 A JP17549481 A JP 17549481A JP S6113429 B2 JPS6113429 B2 JP S6113429B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- transistor
- cathode
- power supply
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 18
- 238000005513 bias potential Methods 0.000 claims 1
- 101150097247 CRT1 gene Proteins 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 101100112083 Arabidopsis thaliana CRT1 gene Proteins 0.000 description 1
- 101100238301 Arabidopsis thaliana MORC1 gene Proteins 0.000 description 1
- 101100519629 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) PEX2 gene Proteins 0.000 description 1
- 101100468521 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFX1 gene Proteins 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
- H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
- H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
- H04N3/20—Prevention of damage to cathode-ray tubes in the event of failure of scanning
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Details Of Television Scanning (AREA)
Description
【発明の詳細な説明】
本発明は、特にテレビジヨン受像機におけるス
ポツトキラー装置に関するもので、特にテレビジ
ヨン受像機の電源投入時の不都合な現象を取除こ
うとするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a spot killer device, particularly in a television receiver, and is particularly intended to eliminate an inconvenient phenomenon when the television receiver is turned on.
第１図に従来の封じ込め型スポツトキラー装置
の基本構成を示す。図において、１はブラウン管
（以下、CRTと略す）、H1，H2はヒータ電極端
子、Ｋはカソード電極端子、G1，G2，G4はおの
おの第１、第２、第４グリツド電極端子である。
また、２は映像出力回路で、その出力端子はカソ
ード電極Ｋに接続されている。Ｖcc1はアースに
対し正電圧の電源端子であり、Ｖcc2は負電圧の
電源端子である。抵抗R1，R2、および可変抵抗
器R4の直列回路が電源端子Ｖcc1，Ｖcc2間に接続
され、可変抵抗器R4の中間端子より抵抗R3を介
して第１グリツド電極G1に直流バイアスが与え
られる。可変低抗器R4はいわゆる輝度調整ボリ
ユームである。なお、電源端子Ｖcc1と第１グリ
ツド電極G1との間にコンデンサC1が接続され、
また抵抗R3に並列にダイオードD1が接続されて
いる。C1がスポツトキラーの役目を果すコンデ
ンサである。またダイオードD1はコンデンサC1
の充電時定数を短縮するためのものである。 FIG. 1 shows the basic configuration of a conventional containment type spot killer device. In the figure, 1 is a cathode ray tube (hereinafter abbreviated as CRT), H 1 and H 2 are heater electrode terminals, K is a cathode electrode terminal, and G 1 , G 2 , and G 4 are first, second, and fourth grid electrodes, respectively. It is a terminal.
Further, 2 is a video output circuit, the output terminal of which is connected to the cathode electrode K. Vcc1 is a positive voltage power supply terminal with respect to ground, and Vcc2 is a negative voltage power supply terminal. A series circuit of resistors R 1 , R 2 and variable resistor R 4 is connected between power supply terminals V cc1 and V cc2 , and is connected to the first grid electrode G 1 from the intermediate terminal of variable resistor R 4 via resistor R 3 . DC bias is applied to. The variable resistor R4 is a so-called brightness adjustment volume. Note that a capacitor C1 is connected between the power supply terminal Vcc1 and the first grid electrode G1 ,
Also, a diode D1 is connected in parallel to the resistor R3 . C1 is a capacitor that acts as a spot killer. Also diode D 1 is capacitor C 1
This is to shorten the charging time constant.
この回路の動作を簡単に説明する。定常動作時
は、コンデンサC1は電源端子Ｖcc1，Ｖcc2間の電
圧を抵抗R1，R4，R2で分圧した電圧に充電され
ている。ここで、テレビジヨン受像機の電源スイ
ツチ（図示せず）をオフにすると両電源端子Ｖcc
１，Ｖcc2およびカソードＫは比較的早い時間内に
アース電位となる。一方、第１グリツド電極G1
には、コンデンサC1が低抗R3を含む電流通路に
て放電が完了する比較的長い時間にわたつて、ア
ースに対して負電圧が加わる。すなわち、CRT1
のカソードＫ〜第１グリツドG1はカツトオフ状
態に保たれ、電源スイツチのオフと同時にテレビ
ジヨン受像機の偏向動作が停止しても輝点（スポ
ツト）が発生することはない。 The operation of this circuit will be briefly explained. During normal operation, the capacitor C 1 is charged to a voltage obtained by dividing the voltage between the power supply terminals V cc1 and V cc2 by the resistors R 1 , R 4 , and R 2 . Here, when the power switch (not shown) of the television receiver is turned off, both power supply terminals V cc
1 , V cc2 and the cathode K reach ground potential within a relatively quick time. On the other hand, the first grid electrode G 1
, a negative voltage is applied to ground for a relatively long period of time during which capacitor C 1 completes its discharge in the current path containing low resistance R 3 . That is, CRT1
The cathode K to the first grid G1 are kept in a cut-off state, and even if the deflection operation of the television receiver is stopped at the same time as the power switch is turned off, no bright spot is generated.
しかしこの従来の回路では、電源スイツチオン
時、コンデンサC1がＶcc1〜C1〜D1〜R4〜R2〜Ｖc
ｃ２の充電路で充電され、その間第１グリツド電位
は相対的に定常時に比べてカソード電位に近いた
め、スイツチオン時、特にオン、オフ、オン等の
繰返しでタイミングによつて形のくずれたラスタ
ーや走査線が異常に明るくCRT面に現われるこ
とがあつて異常感を与えることがある。 However, in this conventional circuit, when the power is switched on, the capacitor C 1 is V cc1 ~ C 1 ~ D 1 ~R 4 ~R 2 ~V c
During the charging path of c2 , the first grid potential is relatively closer to the cathode potential than in the steady state, so when the switch is turned on, the shape of the raster may be distorted depending on the timing, especially when turning on, off, on, etc. Scanning lines may appear abnormally bright on the CRT screen, giving a sense of abnormality.
本発明は上記点に鑑みてなされたもので、スイ
ツチオン時の不都合な現象を取り除くものであ
る。以下その一実施例を第２図、第３図を用いて
説明する。 The present invention has been made in view of the above points, and is intended to eliminate the inconvenient phenomenon at the time of switch-on. An example of this will be described below with reference to FIGS. 2 and 3.
第１の実施例を第２図に示す。なお、図中第１
図と同一の番号、符号のものは同一物を示し、説
明は省略する。 A first embodiment is shown in FIG. In addition, the first
The same numbers and symbols as those in the drawings indicate the same parts, and the explanation will be omitted.
第２図は形の上では第１図よりダイオードD1
を除去し、トランジスタQ1、コンデンサC2、抵
抗R5，R6を追加したものである。すなわち、図
示するように、コンデンサC1と直列にトランジ
スタQ1を接続し、電源端子Ｖcc1とＶcc2との間に
コンデンサC2と抵抗R5，R6の直列回路を挿入す
るとともに、抵抗R5とR6の接続点をトランジス
タQ1のベースに接続したものである。 Figure 2 shows the diode D 1 in shape compared to Figure 1.
is removed, and transistor Q 1 , capacitor C 2 , and resistors R 5 and R 6 are added. That is, as shown in the figure, a transistor Q 1 is connected in series with a capacitor C 1 , a series circuit of a capacitor C 2 and resistors R 5 and R 6 is inserted between power supply terminals V cc1 and V cc2 , and a resistor The connection point between R5 and R6 is connected to the base of transistor Q1 .
第２図の動作を説明すると、スイツチオン時コ
ンデンサC2、抵抗R5により与えられるベース電
流によりトランジスタQ1がオンとなり、第１グ
リツド電極G1をＶcc1の電位に引張つてCRTのカ
ソードＫ〜第１グリツド電極G1間をカツトオフ
にして不都合な現象が現われるのを避けるととも
に、コンデンサC1を急速に充電するものであ
る。なおトランジスタQ1のオン時間はコンデン
サC2、抵抗R5の充電時定数により決められ、コ
ンデンサC2の充電が完了すればトランジスタQ1
はオフとなり、定常状態に入る。以降はスイツチ
オフ時の動作も第１図の従来例と同じである。 To explain the operation of FIG. 2, when the switch is turned on, the transistor Q1 is turned on by the base current given by the capacitor C2 and the resistor R5 , and the first grid electrode G1 is pulled to the potential of Vcc1 , and the CRT cathode K~ The first grid electrode G1 is cut off to avoid undesirable phenomena, and the capacitor C1 is rapidly charged. Note that the on-time of transistor Q 1 is determined by the charging time constant of capacitor C 2 and resistor R 5 , and when charging of capacitor C 2 is completed, transistor Q 1
turns off and enters steady state. Thereafter, the operation at the time of switch-off is also the same as that of the conventional example shown in FIG.
以上のように第２図の構成によれが、封じ込め
型スポツトキラー回路におけるスイツチオン時の
不都合な現象を解消しるものである。 As described above, the configuration shown in FIG. 2 eliminates the inconvenient phenomenon at the time of switch-on in the containment type spot killer circuit.
第３図は他の実施例を示すもので、CRT1を第
１グリツドドライブ方式として、CRT1のカソー
ドにて輝度コントロールおよびスポツトキラー動
作をさせるものである。もちろん、第２図と同様
の作用効果を得ることができる。 FIG. 3 shows another embodiment in which the CRT 1 is of the first grid drive type and the cathode of the CRT 1 performs brightness control and spot killer operation. Of course, the same effects as in FIG. 2 can be obtained.
以上説明したように本発明によれば、封じ込め
型スポツトキラー回路において、電源スイツチオ
ン時、トランジスタをオンせしめることによつて
コンデンサを瞬時に充電せしめ、充電が完了した
後、トランジスタをオフせしめて定常状態に移行
せしめることにより、スイツチオン時の不都合な
現象を確実に防止することができるものである。 As explained above, according to the present invention, in a containment type spot killer circuit, when the power supply is switched on, the transistor is turned on to instantly charge the capacitor, and after charging is completed, the transistor is turned off to maintain a steady state. By making the transition to , it is possible to reliably prevent inconvenient phenomena at the time of switch-on.
第１図は従来例のスポツトキラー装置の回路
図、第２図、第３図はおのおの本発明の一実施例
におけるスポツトキラー装置の回路図である。
１……ブラウン管、Q1……トランジスタ、
C1，C2……コンデンサ、R1，R2，R3，R5，……
抵抗、R4……可変抵抗器。
FIG. 1 is a circuit diagram of a conventional spot killer device, and FIGS. 2 and 3 are circuit diagrams of a spot killer device according to an embodiment of the present invention. 1... Braun tube, Q 1 ... Transistor,
C 1 , C 2 ... Capacitor, R 1 , R 2 , R 3 , R 5 , ...
Resistance, R 4 ...variable resistor.
Claims (1)
のコンデンサとトランジスタの直列回路を挿入
し、前記トランジスタのコレクタと第１のコンデ
ンサの接続点をブラウン管の第１グリツドまたは
カソードに接続し、前記トランジスタのベースと
いずれか一方の電源端子との間に、電源投入時に
前記トランジスタを過渡的に導通せしめて前記ブ
ラウン管の第１グリツド−カソード間の逆バイア
ス電位差を大ならしめ前記ブラウン管をカツトオ
フさせる時定数回路を構成する第２のコンデンサ
と抵抗を接続してなるスポツトキラー装置。1 Between the first and second power supply terminals that are different from each other,
A series circuit consisting of a capacitor and a transistor is inserted, the connection point between the collector of the transistor and the first capacitor is connected to the first grid or cathode of the cathode ray tube, and between the base of the transistor and one of the power supply terminals. , a resistor is connected to a second capacitor constituting a time constant circuit that makes the transistor conductive transiently when power is turned on to increase a reverse bias potential difference between the first grid and the cathode of the cathode ray tube, and cuts off the cathode ray tube. A spot killer device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17549481A JPS57103472A (en) | 1981-10-30 | 1981-10-30 | Spot killer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17549481A JPS57103472A (en) | 1981-10-30 | 1981-10-30 | Spot killer device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57103472A JPS57103472A (en) | 1982-06-28 |
| JPS6113429B2 true JPS6113429B2 (en) | 1986-04-14 |
Family
ID=15997016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17549481A Granted JPS57103472A (en) | 1981-10-30 | 1981-10-30 | Spot killer device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57103472A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61176861U (en) * | 1985-04-19 | 1986-11-05 | ||
| JPS6462084A (en) * | 1987-09-02 | 1989-03-08 | Anritsu Corp | Spot killer circuit for crt |
-
1981
- 1981-10-30 JP JP17549481A patent/JPS57103472A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57103472A (en) | 1982-06-28 |
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