JPH0130346B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for automatically erasing an image in a television receiver when no received signal is received.

First, the brightness control circuit currently used in general television sets will be explained. FIG. 1 is a circuit diagram of a general configuration of a brightness control circuit of a signal processing IC.

In this circuit, a luminance signal (Y signal) is input from the common emitter terminal of transistors Q ₆ and Q ₇ ,
The contrast is controlled by contrast control voltages applied to the bases of these transistors Q ₆ and Q ₇ , and the output is taken out from the collector of transistor Q ₉ .

The extracted luminance signal is sent to an amplifying transistor.
The signal is supplied to the color demodulation matrix circuit via _Q11 and _Q12 . At the same time, the luminance signal taken out from the collector side of transistor Q ₉ is transmitted to transistor Q ₁ ,
A pedestal clamp circuit consisting of Q ₂ , Q ₃ , Q ₄ , Q ₅ , Q ₁₄ , Q ₁₃ and a capacitor C ₁ controls the DC level (brightness level) of the luminance signal.

To briefly explain the basic operation of this pedestal clamp circuit, the luminance signal appearing on the collector side of transistor _Q9 passes through transistor _Q10 and appears at the emitter of transistor _Q10 . A negative pedestal clamp pulse is applied to the base of transistor _Q1 . Therefore, transistor _Q1 conducts only during the clamp pulse period,
A switch circuit consisting of switching transistors Q ₂ and Q ₃ becomes conductive, and the pedestal level of the luminance signal appearing at the emitter of transistor Q ₁₀ is held in capacitor C ₁ .

Transistors Q ₄ and Q ₅ constitute a comparator, and a brightness control voltage is applied to the base of transistor Q ₅ , and a capacitor C ₁
The voltage of the pedestal portion of the brightness signal held at the brightness control voltage is compared with the brightness control voltage.

At this time, if the base potential of transistor _Q5 is higher than the potential held in capacitor _C1 , the collector current of transistor _Q5 decreases, and the base potential and emitter potential of transistor _Q14 also decrease.
The base potential of transistor _Q13 decreases and its collector current also decreases. Therefore, the collector potential of transistor Q ₉ increases and the potential of transistor Q ₁₀ increases.
The DC level of the luminance signal appearing at the emitter of C1 increases, and the potential across capacitor _C1 also increases,
Stabilization occurs when the base potentials of transistors Q ₄ and Q ₅ become equal.

Conversely, when the base potential of transistor _Q5 is lower than the base potential of transistor _Q4 , the potential of capacitor _C1 decreases.
It becomes stable when both base potentials of Q ₄ and Q ₅ become equal.

In this way, by changing the brightness control voltage, the pedestal level of the brightness signal can be controlled, the DC level can be adjusted, and the brightness can be adjusted. Furthermore, the resistor _R2 is a resistor that determines the time constant of the clamp circuit.

However, in general, in the case of the circuit configuration shown above, even in the absence of a received signal (in the absence of a brightness signal and clamp pulse), the average value of the signal is stored at both ends of the capacitor _C1 . A corresponding DC level is applied via resistors R ₁ and R ₂ , and by changing the brightness control voltage, the potential across the capacitor C ₁ also changes, and the DC level at the emitter of the transistor Q ₁₂ also changes. Therefore, there is a drawback that when the brightness control voltage is set at a high level and there is no signal, the screen is not completely blanked out and a white raster appears.

Therefore, the present invention aims to provide a circuit that can completely blank out and erase the screen when there is no received signal, and the present invention will be described below along with one embodiment.

In this circuit, the presence or absence of a received video signal is determined by the presence or absence of an output signal from the synchronization separation circuit.

The output circuit of the synchronous separation signal differs depending on the method, but generally it is as shown in Figures 2 and 3.
When there is no input video signal to the sync separator SS, the output voltage is equal to the circuit power supply voltage,
If an input video signal is present, an output signal approximately equal to 0V is output only during the synchronization signal period.

In this circuit, a switching circuit S is connected to the output side of the synchronous separation circuit SS, as shown in FIG. In the figure, _C2 is a clamping capacitor, _D1 is a clamping diode, and _R3 is a discharging resistor for capacitor _C2 . Further, D ₂ is a switching diode, R ₄ is a protection resistor, and R ₅ is a clamp current limiting resistor. This resistor _R5 may be omitted. A capacitor C ₁ and a resistor R ₃ are connected in parallel, a diode D ₁ is connected to them, and one end of the series circuit is connected to a power supply terminal V _CC at a constant potential. The other end is connected to the synchronous separation output terminal via diode _D1 and resistor _R5 .

In the above configuration, the potential at the intersection (point A) of the anode side of the clamping diode D ₁ with the resistor R ₃ and the capacitor C ₂ is connected to the sync separation circuit SS because there is no sync separation output signal when there is no signal. Since the potential at point A is equal to the power supply voltage (V _CC ), the potential at point A also becomes V _CC .

However, under normal reception conditions, the output voltage of the sync separator SS has a pulse waveform as shown in Figure 2, and during the sync signal period, diode D ₁ conducts and capacitor C ₂ charges. As a result, the potential at point A drops below V _CC . Synchronous separation circuit
If the output impedance of SS is sufficiently low and the resistance _R5 is small, the potential at point A will drop to almost 0V, but in reality, as a clamp current flows, the voltage of the synchronous separation output signal also decreases. , it is not possible to flow a large clamp current due to the increase in voltage, but in normal operating conditions the A point can be easily set to approximately 1/2V _CC .

On the other hand, the gain of the brightness control circuit is ABL
The brightness control voltage is normally set very high due to its relationship with the circuit, and the control range of the brightness control voltage is very narrow. Therefore, the potential change range of the capacitor _C1 for holding the pedestal clamp voltage is also very narrow.

Therefore, the brightness setting potential in normal reception conditions is set to a dotted point between V _CC and 1/2V _CC , and the voltage at point A is connected to the brightness setting potential through diode D ₂ and resistor R ₄ for the switching circuit. Connect to the holding capacitor _C1 of the control circuit.

In that case, under normal reception conditions, the voltage at point A is approximately 1/2V _CC , and the potential of capacitor _C1 is higher than that, so diode _D2 is cut off and has no effect on brightness control operation. There isn't.

On the other hand, when there is no input video signal and there is no signal, the voltage at point A will change as described above.
The voltage becomes V _CC , and diode D ₂ becomes conductive, raising the potential of capacitor C ₁ to V _CC . The operation of the circuit shown in Figure 1 when the potential of capacitor C ₁ is forcibly raised to V _CC from the outside in this way is that the base potential of transistor Q ₄ is raised, so that the brightness control voltage ( This results in the same state as if the base potential of transistor _Q5 was lowered, and the operation of the circuit shifts in the direction of lowering the base potential of transistor _Q4 , resulting in the screen being erased. In this way, when the received signal disappears, the image can be erased and unnecessary display on the screen can be eliminated.

Incidentally, in the case where the polarity of the output signal of the synchronization separation circuit SS is opposite to that described above, a circuit configuration as shown in FIG. 3 may be used. In the figure, the potential at point B is 0V when there is no signal, and can be set to about 1/2V _CC during normal operation. Therefore, the control range of brightness control is set to 0V.
to 1/2V _CC , and connect the diode
A similar effect can be obtained by comparing the polarity of D ₂ as shown in Figure 2, connecting it in the opposite direction, and connecting it to the base of transistor Q ₅ to which the brightness control voltage is applied through resistor R ₄ . Can be done.

As described above, according to the present invention, it is possible to obtain a useful image erasing circuit that can automatically completely erase an image when the received signal disappears, and does not cause unsightly noise screens or white rasters to appear. It is something that can be done.

[Brief explanation of drawings]

1, 2, and 3 are circuit diagrams of an image erasing circuit in one embodiment of the present invention. BC……Brightness control circuit, Q ₁ , Q ₂ , Q ₃ ,
Q ₄ , Q ₅ , Q ₁₀ , Q ₁₄ ... Transistor, C ₁ ... Holding capacitor, SS ... Synchronous separation circuit, C ₂ ...
Capacitor, R ₃ , R ₄ , R ₅ ... Resistor, D ₁ , D ₂ ...
diode.

Claims (1)

[Claims] 1. A transistor to which a contrast-controlled luminance signal is applied to the base, a capacitor for pedestal level clamping, and a switch circuit inserted between the output terminal of the transistor and the capacitor, which is conductive only during the period when the pedestal clamp pulse is applied. , a pedestal clamp circuit comprising a comparator to which a brightness control voltage is applied to one base and a voltage across the capacitor to the other base; and when the brightness control voltage is higher than the potential of the capacitor, the brightness signal is DC-controlled. A brightness control circuit that increases the level to increase the potential of the capacitor, and when the brightness control voltage is lower than the potential of the capacitor, lowers the potential of the capacitor, and controls so that it becomes stable when both base potentials become equal. A diode is connected in series to a parallel circuit of a resistor and a capacitor, one end of which is connected to a certain reference potential point, and the other end is connected directly to the output end of the synchronous separation circuit or by connecting a resistor. The intersection of the resistor and capacitor connected in parallel with the diode is connected to the brightness control circuit or the pedestal clamp circuit through a switching circuit such as a diode or transistor to erase the image when there is no signal. An image erasing circuit characterized in that: