JPS6364931B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a relay fault detection method for searching for faults in repeaters in a relay transmission line.

Conventionally, multiple repeaters were used in the transmission line.
The PC01 relay transmission system is known. One such transmission method is to assign two types of 2-bit codes "01", "10" and "11", "00" to each "1" and "0" of the input signal, DMI (differential mark) converts the input signal so that the sign of the first bit of the 2-bit code is different from the sign of the last bit of the immediately preceding 2-bit code.
inversion; differential mark inversion) sign or “1”
A transmission method using dipulse, which is a code in which 2-bit codes "01" and "10" are assigned to each "0", has been proposed to simplify the repeater configuration and facilitate error detection. has been done. However, no proposal has been made regarding a repeater failure detection method in such a transmission system.

An object of the present invention is to provide a fault detection method for a repeater in a relay transmission system.

Next, the present invention will be explained in detail with reference to the drawings.
First, the principle of the present invention will be described. As shown in Figure 1
Connect the output of the DMI code converter 1 to the first input terminal 20 of the exclusive OR circuit (EX-OR) 21,
After passing the exclusive OR output through a circuit 22 that delays it by 1 bit, it is applied to the second input terminal 25 of EX-OR 21. The circuit including this EX-OR21 has the function of a sign integration circuit, that is, a flip-flop circuit built into the repeater. Here, the DMI code conversion rule is shown in the transition diagram shown in FIG. In this figure, the symbols in circles indicate DMI converter outputs, and the symbols on the line with arrows indicate DMI converter inputs. This DMI code corresponds to “1” and “0”
Two types of 2-bit codes “10”, “01” and “11”, “00” are assigned to each of They are becoming different from each other. still,
It is also possible to make the input codes "1" and "0" correspond to the DMI code in the opposite way to the above, and the following explanation also holds true in this case.

FIG. 3 shows the terminals 20 and 30 when "1" and "0" are applied to the terminal 10 in FIG.
Indicates the sign that appears in For one input, each output terminal can output two types of codes depending on the previous output code. For example, if terminal 10 is “1”,
When terminal 20 is “10”, exclusive OR input 2
Different code conversions are performed depending on whether the output code of No. 5, that is, the output code of the previous bit at the terminal 30 is "1" or "0". When the output line 25 is "0", it becomes "11", and when it is "1", it becomes "00". In FIG. 1, terminal 10
Assume that when the code of terminal 20 is "1" and the code of terminal 20 is "10", the code of terminal 30 is "11". At this time, when the code "1" is given to the input terminal 10, the terminal 20 becomes "10" according to the transition diagram of FIG. 2, and the terminal 30 becomes "00" considering the previous time slot code "11". On the other hand, when the terminal 10 becomes "0" under the same conditions, the terminal 20 becomes "11" from FIG. 2, and the terminal 30 becomes "01" considering the immediately preceding code. Therefore, it can be seen that there is a transition from "11" to "01" and "00". Similarly, the fourth
Get the picture. Here, consider code conversion as shown in FIG. This code conversion assigns two 2-bit mode codes “11”, “01” and “10” and “00” corresponding to “1” and “0”, and the code mode is the same as the previous code mode. shall be assigned different polarities. The code obtained by this code conversion is the fourth
It is clear that it satisfies the transition diagram in the figure, and has the same sign rule as the sign of the terminal 30 in FIG. Furthermore, the mark rate of the input code corresponds to the mark rate of the output code. That is, assuming that each bit of the input code is independent of each other, when the input code mark rate is m, the mark rate of the output code is 2/1 (2/1+m), which corresponds linearly to the input code mark rate.

FIG. 6 is a block diagram illustrating a fault search method of the present invention in which the code converter 3 that performs the conversion shown in FIG. 5 is used to search for faults. The code transition at the code conversion output terminal 30 is the same as the code transition in FIG. It is known that the transfer function of the cascade connection of the integrating circuit 2 shown in FIG. 1 and the differentiating circuit 4 shown in FIG. 6 is 1 or -1. Therefore, terminal 30
By passing the output from sign differentiation circuit 4,
The same code string as terminal 20 in FIG. 1, that is, the output of terminal 40 becomes a code string that satisfies the DMI code rule. The code at the output terminal 40 of the fault search code generator 7 satisfies the DMI rule as described above, and this output is sent to the transmission line 45. Reference numeral 6 represents a repeater in the transmission path, and reference numeral 61 represents a regenerative repeater circuit. A flip-flop 5 is connected to the relay circuit 61, and an output signal used for fault searching is obtained at an output terminal 80. Since the output code of the relay circuit 61 is regenerated and relayed, it becomes the same as that at the terminal 40, and at the output terminal 80 of the flip-flop 5, a code string having the same code rule as the terminal 30 in FIG. 1 is obtained. Further, the magnitude of the mark rate of the code string outputted to the terminal 80 corresponds linearly to the magnitude of the mark rate of the code string inputted to the input terminal 50 of the code converter 3. Therefore, the code generator 65 generates a code string with a biased mark rate (the mark rate is not 1/2) at the terminal 60.
If you connect a so-called specified frequency generator 75 with a long period of several kHz to the terminal 70, EX-
At the output terminal 50 of the OR6, a code string whose mark rate changes at a period of a designated frequency is obtained. This code string is passed through a code converter 3 and a differentiation circuit 4,
When sent to the transmission line 45 as the output of the fault search signal generator 7, a code whose mark rate changes in accordance with the terminal 50 is obtained at the output terminal 80 of the flip-flop 5 built in the repeater 6. By passing this code string through a low-pass wave filter 53, a specified frequency can be obtained from the code string. If an error occurs in the transmission path, the internal state of the flip-flop 5 changes, so the phase of the low frequency pass wave filter output 90 changes with each error, or the designated frequency component becomes smaller.

FIG. 7 shows an example of codes for each part in FIG. 6. Figure 7 a, b, c, d are terminals 60, 7 in Figure 6, respectively.
Represents outputs of 0, 50, and 30. 7e represents the output of the terminal 43 of the delay circuit 42, and f and g represent the code strings of the terminals 40 and 80, respectively. In this example, the output code string a of the code generator 65 has a mark rate of about 30%, and after passing through EX-OR6, the mark rate becomes small in the first half and large in the second half, as shown in c. There is. Repeater flip-flop output 80
Also, the mark rate in the first half is small, and the mark rate in the second half is large. When this code string is passed through the low-pass wave generator 53, a low frequency component such as h is obtained. Here, f
If an error occurs as shown by the broken line in g, the output appearing at the output terminal 80 of the flip-flop of the repeater will have an inverted sign after the error occurs, as shown by the broken line in g. Therefore, the output h of the low-pass wave generator 53 at this time has a waveform as shown by the broken line, in which the phase changes significantly at the time when the error occurs. Alternatively, as the number of errors increases, the designated frequency component becomes smaller. This signal h is transferred to the station building using an intervening line of the transmission line, and at the station building,
By monitoring the phase change or designated frequency level of the signal, repeater errors can be monitored.

FIG. 8 is a circuit diagram showing one embodiment of the present invention. Fault search pattern generator 7 has a mark rate of 1/2
The circuits 65 and 75 are connected to the input terminals 60 and 70 of EX-OR6, respectively, and are connected to the output terminal 50 of EX-OR6. A signal in which the mark rate changes at a period of a specified frequency is obtained. A clock signal is available at the output terminal 95 of the code generator 65. Next, the code conversion circuit 3 will be explained in detail. It has already been mentioned that the code conversion rule of this conversion circuit is shown in FIG. 5, and the code transition of the output is shown in FIG. According to this code conversion rule, the previous bit of a 2-bit code set represents a code different from the previous bit of the immediately preceding 2-bit code set. That is, the previous bit alternately repeats "1" and "0".
On the other hand, the rear bit directly represents the input code of this code conversion circuit. Considering the characteristics of the code conversion rule described above, in FIG. has been created. On the other hand, the rear bit is created by reading out the input code in the D type flip-flop 31 using the clock signal from the terminal 95 and matching the phase of the input code with the clock.

The frequency-divided signal representing the previous bit and the input code representing the subsequent bit, which are generated separately as described above, are logically summed with the clock signal at gates 32 and 34, respectively, and thereby the input code and the divided signal of the NRZ are logically summed. The frequency signal is converted into an RZ pulse with a pulse width of 50%. Moreover, at this time, the phases of the clock signals supplied to the gates 32 and 34 are out of phase with each other by 180 degrees, so the phase of each gate 32 and 34 is also shifted by 180 degrees.
It is shifted by 180°. That is, during a half cycle in which the pulse train of the gate output is always zero, the other gate output is not always "0". Therefore, both gates 32
By passing the outputs of 34 and 34 through an OR gate, the previous bit and the subsequent bit are added, and the desired code conversion can be performed. The code conversion circuit 3 generates the code in the AND gate 32 and the mode in the AND gate 34, since the bit after the 2-bit code represents the code and the previous bit represents the mode. , sign conversion is performed by adding with an OR gate. As a result, a code satisfying the DMI code rule is generated at the output terminal 40 of the differentiating circuit 4. The search pattern from the search pattern generator passes through the transmission line 45 and is regenerated and relayed by the repeater 6. An output code and a clock signal are obtained from the output terminals 62 and 63 of the repeater circuit 61, respectively, and by applying both to the AND gate 55, an RZ code is created, and this code is applied to the flip-flop 5.
Flip the AND gate 55 and flip-flop 5 is the sixth
Performs the same code conversion as code integration circuit 5 in the figure, and
The input sign of the sign integration circuit 5 in the figure is the terminal 6 in FIG.
The output sign from 2 is the same as that from 2. The output of flip-flop 5 is supplied to low pass filter 53 and the specified frequency is reproduced at terminal 90. As mentioned above, if an error occurs in the repeater, the low frequency signal at terminal 90 will undergo a phase change. Repeater errors can be monitored by transmitting this signal to a station or the like via an intervening line 92 of the transmission line and detecting a phase change at the station or the like. still,
As in this embodiment, a band pass filter (BPF) 9 is installed between the repeater monitoring signal output terminal 90 and the intervening line 92.
When 1 is inserted, a monitoring signal is transmitted to the intervening line 92 only when the designated frequency of the search pattern generator matches the passing frequency of the BPF 91. If you change and set the center frequency of this BPF for each repeater,
You can select repeaters to monitor by changing the designated frequency.

As described above, according to the present invention, a repeater failure search pattern that does not disturb the DMI coding rule can be obtained. Therefore, since it is possible to search for a code that satisfies the DMI rule for a repeater circuit that normally transmits a DMI signal, the present invention has the feature that the evaluation of the repeater is based on reality. Furthermore, since it is known that the code transitions of DMI and Dipulse are the same, this monitoring method is also effective for Dipulse transmission lines.

In the above embodiments, the designated frequency was limited to a single frequency, but it is clear that even if various signals are used as the designated frequency, the designated frequency will be reproduced in the repeater monitoring output. It is also possible to set the specified frequency as the specified frequency.

[Brief explanation of drawings]

Figure 1 is a configuration diagram in which a DMI conversion circuit and a flip-flop counting circuit are connected in cascade, and Figure 2 is
DMI code transition diagram, Figure 3 is terminal 10 in Figure 1
4 is a code transition diagram at the terminal 30 in FIG. 1, FIG. 5 is a diagram showing the input/output correspondence of the code conversion circuit used in the present invention, and FIG. FIGS. 7a to 7h are diagrams showing the configuration of the present invention, and FIG. 8 is a circuit diagram showing an embodiment of the present invention. In Figures 6 and 8,
5, 31, 33...flip flop, 30...
... Code converter output terminal, 42, 52 ... 1-bit delay circuit, 41, 51 ... Exclusive OR circuit, 6
5... code generator, 75... specified frequency generator,
6...Repeater, 61...Regenerative relay circuit, 53...
Low pass filter, 91...Band pass filter,
7...Fault search code generator.

Claims (1)

[Claims] 1. In a relay fault detection method in which fault detection is performed by transmitting a fault detection signal to a repeater using a differential mark inversion code or dipulse, "1" which is appropriately and sufficiently different from 0.5 is m. means for generating a first code string by controlling two states of the occurrence probability of "1" and the occurrence probability of "1" (1-m) by a repeater specified frequency signal having a predetermined period; 2 bits corresponding to each bit in the string, the trailing bit being composed of bits having the same contents as each bit of the first code string, and the preceding bit being composed of bit contents opposite to the contents of the immediately preceding bit. code converting means that continuously generates a code consisting of a second code string and outputs a second code string; a code for one bit of the second code string;
code differentiating means for generating a differential code that is an exclusive OR with the code immediately before the bit as a search code for sending out to a transmission path; a means for receiving the search code; a transfer function of the code differentiator; The product of is 1 or -
code integrating means for integrating the received search code having a transfer function of 1; extracting the component of the repeater specified frequency signal from the output signal of the code integrating means; and extracting the component at the sending point of the search code. 1. A relay failure detection method, which includes means for receiving relay designated frequency components and searching for failures in a relay transmission system. 2. In a search code generator for a relay fault search method in which a fault search signal is transmitted to a repeater using a differential mark inversion code or dipulse to search for faults, a first means for obtaining a code having an occurrence probability of ``; a second means for inverting and controlling the code obtained by the first means using the repeater specified frequency signal; and an output code of the second means. Corresponding to each bit, a code consisting of 2 bits is generated, in which the trailing bit has the same content as each bit of the output code, and the leading bit has the opposite bit content from the immediately preceding bit. 1. A fault search code generation device comprising: a code conversion circuit; and means for calculating an exclusive OR of an output code of the code conversion circuit and a code obtained by delaying the output code by 1 bit.