JPS6364353A - Hybrid integrated circuit device and formation of electric resistance in hybrid integrated circuit substrate - Google Patents
Hybrid integrated circuit device and formation of electric resistance in hybrid integrated circuit substrateInfo
- Publication number
- JPS6364353A JPS6364353A JP61208474A JP20847486A JPS6364353A JP S6364353 A JPS6364353 A JP S6364353A JP 61208474 A JP61208474 A JP 61208474A JP 20847486 A JP20847486 A JP 20847486A JP S6364353 A JPS6364353 A JP S6364353A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- resistance
- trimming
- printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 11
- 230000015572 biosynthetic process Effects 0.000 title description 6
- 238000009966 trimming Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 10
- 238000007639 printing Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009957 hemming Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は基板上に印刷抵抗からなる電気抵抗を有する薄
膜又は厚膜の混成集積回路装置と、基板上に印刷抵抗か
らなる電気抵抗を形成する薄膜又は厚膜の混成集積回路
基板における電気抵抗の形成方法に関するものである。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a thin film or thick film hybrid integrated circuit device having an electrical resistance made of a printed resistor on a substrate, and a method for forming an electrical resistance made of a printed resistor on a substrate. The present invention relates to a method for forming electrical resistance in a thin film or thick film hybrid integrated circuit board.
薄膜又は厚膜の混成集積回路装置（ハイブリッドＩｃ）
では、例えばアルミナ、ガラス、プラスチック等の絶縁
基板上に導体と抵抗を、主として膜の状態で形成して作
成される。そして、これに能動素子としてトランジスタ
、ダイオード等が取り付けられた後に、プラスチック、
金属等の容器に封入される。Thin film or thick film hybrid integrated circuit device (hybrid IC)
In this case, a conductor and a resistor are formed mainly in the form of a film on an insulating substrate made of, for example, alumina, glass, or plastic. After transistors, diodes, etc. are attached as active elements to this, plastic,
Enclosed in a container such as metal.
このような混成集積回路基板にお（）る電気抵抗の形成
は、一般には印’ｉｊ：１法によってなされる。第４図
はこの印刷法による抵抗形成をに（明する平面図である
。同図において、絶縁性の基板１上に形成された一対の
導体端子２ａ、 ２ｂ間には、ｉ［Ｊ ！＋ｌｌ抵抗３
として抵抗材料が印刷される。ところが、この印１則低
抗３の抵抗値は、材料、印１ｆす条件、焼成条件等によ
って同−設計のものでもバラツキが生じる。このバラツ
キは小さければ小さいほど望ましいが、実用的には１０
％以下に抑えるのが困難である。そこで、従来からトリ
ミングと呼ばれる抵抗ｐ正がなされている。The formation of electrical resistance in such a hybrid integrated circuit board is generally performed by the ij:1 method. FIG. 4 is a plan view illustrating the formation of a resistor by this printing method. In the same figure, there is an i[J!+ll resistance 3
The resistive material is printed as However, the resistance value of the resistance value 3 of the mark 1 rule varies depending on the material, the conditions of the mark 1f, the firing conditions, etc. even for those of the same design. The smaller this variation is, the more desirable it is, but in practice it is
It is difficult to keep it below %. Therefore, a positive resistance p has been conventionally used, which is called trimming.
第５図はこのトリミングを説明するための平面図である
。図示の如く、印刷抵抗３に切り込み部４を形成し、こ
れによって正確な抵抗値制御を行なっている。なお、切
り込み部４の形成は例えば回転式ヤスリ、サンドブラス
ト、レーザ等によりなされる。FIG. 5 is a plan view for explaining this trimming. As shown in the figure, a notch 4 is formed in the printed resistor 3, thereby accurately controlling the resistance value. Note that the cut portion 4 is formed by, for example, a rotary file, sandblasting, laser, or the like.
（発明が解決しようとする問題点〕
しかしながら、トリミングにより印Ｎ１１ｉＪ低杭の値
をある設定値に調整するとき、１〜リミング゛帖痕によ
っては１氏抗１直にドリフトを生じることかある。(Problems to be Solved by the Invention) However, when the value of the mark N11iJ low stake is adjusted to a certain set value by trimming, a drift may occur in one direction depending on the rimming mark.
このため、ドリフト量によっては再びトリミングをする
必要が生じたり、印刷抵抗自体が不良となる場合があり
、従って製品のコスト上昇等を招いている。Therefore, depending on the amount of drift, it may be necessary to perform trimming again, or the printed resistor itself may become defective, leading to an increase in the cost of the product.
そこで本発明は、設定値に対して粘度よく制すロされた
抵抗値の電気抵抗を有する混成集積回路装置と、トリミ
ングによる印刷抵抗の調整を正確かつ容易に行なえる混
成集積回路基板における電気抵抗の形成方法とを提供す
ることを目的とする。Therefore, the present invention provides a hybrid integrated circuit device having an electrical resistance with a resistance value that is well controlled with respect to a set value, and an electrical resistance in a hybrid integrated circuit board that allows the printed resistance to be adjusted accurately and easily by trimming. The purpose is to provide a forming method.
本発明に係る混成集積回路装置は、基板上の一対の端子
間に、複数の印刷抵抗を並列に配設してなる所定抵抗値
の電気抵抗を有することを特徴とする。The hybrid integrated circuit device according to the present invention is characterized in that it has an electric resistance of a predetermined resistance value, which is formed by arranging a plurality of printed resistors in parallel between a pair of terminals on a substrate.
また、本発明に係る混成集積回路基板にあける電気抵抗
の形成方法は、基板上の少なくとも一対の端子間に複数
の印刷抵抗を並列に形成する第１のステップと、複数の
印刷抵抗のうちの少なくとも１つを残して他の印１伺抵
抗をトリミングする第２のステップとを扁えることを特
徴とする。Further, the method for forming electrical resistors in a hybrid integrated circuit board according to the present invention includes a first step of forming a plurality of printed resistors in parallel between at least one pair of terminals on the board; and a second step of trimming all but one of the resistors.
（作用〕
本発明に係る混成集積回路装置は、以上のＪ、うに（１
カ成されるので、複数の印刷抵抗、全体としての電気抵
抗の、トリミング後の抵抗値ドリフ１〜を低く抑えるよ
うに動く。(Operation) The hybrid integrated circuit device according to the present invention includes the above J, Uni (1)
Therefore, the resistance value drift 1~ of the plurality of printed resistors and the electrical resistance as a whole after trimming is kept low.
また、本発明に係る混成集積回路基板における電気抵抗
の形成方法は、以上のにうに構成されるので、第１のス
テップは複数の印刷抵抗からなる電気抵抗を基板上に形
成するように勧ぎ、第２のステップは一部の印刷抵抗の
トリミングによって、全体としての電気抵抗の調整精度
を向上させるように動く。Furthermore, since the method for forming electrical resistance on a hybrid integrated circuit board according to the present invention is configured as described above, the first step is to form electrical resistance consisting of a plurality of printed resistances on the substrate. , the second step operates to improve the tuning accuracy of the overall electrical resistance by trimming some of the printed resistors.
以下、添付図面の第１図および第２図を参照して本発明
の詳細な説明づる。なｄ３、第３図および第４図の従来
例と同一の要素には同一の符号を付し、干祝する説明を
省略する。The present invention will now be described in detail with reference to FIGS. 1 and 2 of the accompanying drawings. d3, the same elements as those in the conventional example shown in FIGS. 3 and 4 are given the same reference numerals, and detailed explanations will be omitted.
第１図は実施１ｒ、すによる印■り抵抗の形成を説明す
る平面図で必り、第２図はこれにトリミングを行った後
の平面図である。第１図に示す如く、本実施例における
電気抵抗は、端子２ａ、 ２ｂ間に並列に形成された２
本の印刷抵抗３ａ、３ｂによって構成されている。この
印刷抵抗３ａ、３ｂの抵抗値が°精度Ｊ、く制御されて
いるとぎは、改めてトリミングを行う必要がなく、従っ
て基板１上に各種能動素子等が配設されて混成集積回路
装置が完成される。FIG. 1 is a plan view illustrating the formation of a marked resistor according to the first embodiment, and FIG. 2 is a plan view after trimming. As shown in FIG. 1, the electrical resistance in this embodiment is determined by two
It is composed of printed resistors 3a and 3b. Since the resistance values of the printed resistors 3a and 3b are controlled with precision J, there is no need to perform trimming again, and therefore various active elements etc. are arranged on the substrate 1 to complete the hybrid integrated circuit device. be done.
設定値にバラツキのあるものについては、第２図に示す
ようにトリミングを行う。すなわら、一方の印刷抵抗３
ａについて切り欠き部４を形成する。このとぎ、他方の
印刷抵抗３ｂについては河らトリミングを行うことなく
、放置しておく。If the set values vary, trimming is performed as shown in FIG. That is, one printed resistor 3
A notch 4 is formed at point a. At this point, the other printed resistor 3b is left alone without being trimmed.
次に、上記実施例の作用を、従来例と比較して説明する
。第４図の従来例において、１ヘリミング前の印刷抵抗
３の抵抗値ＲをＲ３＝Ｒとし、これに対して抵抗値をΔ
ｒだ【プ変動させる１〜リミングを施して第５図のよう
にすると、トリミング後（第５図）の印刷抵抗３の抵抗
１ｉＵ−はＲＡ＝Ｒ＋Δｒ ・・・（１
）となる。Next, the operation of the above embodiment will be explained in comparison with a conventional example. In the conventional example shown in FIG. 4, the resistance value R of the printed resistor 3 before hemming is set to R3=R, and the resistance value
If you apply rimming to make it as shown in Figure 5, the resistance 1iU- of the printed resistor 3 after trimming (Figure 5) is RA=R+Δr...(1
).
一方、第１図の実施例において、トリミングｉ’＋ｉｉ
の印〜ｔ１］抵抗３ａ、３ｂの抵抗１直をそれぞれｒ、
。On the other hand, in the embodiment of FIG. 1, trimming i'+ii
mark ~ t1] The resistors 3a and 3b are connected by r, respectively.
.
ｒｂとし、これらの並列抵抗ＲＢ＠Ｒ３＝Ｒどし、ｈす
ｒ’、＝ｒｂとすると、トリミング前の並列３１−を抗
ＲＢは
ＲＩ３＝ｒ −ｒｂ／（ｒ、＋ｒｂ）＝ｒ、／２＝ｒ
ｂ／２＝Ｒ−（２＞
となる。すなわち、第４図の従来例の印刷抵抗３と比べ
て、第１図の印刷抵抗３ａ、３ｂはそれぞれ２倍の抵抗
値を有する。そこで、この印刷抵抗３ａにトリミングを
施して仝休の並列抵抗値ＲＡを
ＲＡ−Ｒ＋Δｒ・・・（３）
にしＪ：うとしたとき、抵抗値変動がトリミング前の抵
抗値に比例すると仮定すると、印刷抵抗３ａの抵抗値の
変動は第５図の従来例の２１）Ｓｖなわち２Δｒとなる
。rb, and if these parallel resistances RB@R3=R and hsr',=rb, then the parallel resistance 31- before trimming is RI3=r -rb/(r,+rb)=r,/ 2=r
b/2=R-(2>.In other words, compared to the conventional printed resistor 3 in FIG. 4, the printed resistors 3a and 3b in FIG. 1 each have twice the resistance value. When the printed resistor 3a is trimmed to make the idle parallel resistance value RA to be RA-R+Δr...(3), assuming that the resistance change is proportional to the resistance value before trimming, the printed resistor 3a The variation in the resistance value of the conventional example shown in FIG. 5 is 21)Sv, that is, 2Δr.
その結果、上記式（２＞、（３）によって、印刷抵抗３
ａ、３ｂの並列抵抗の抵抗１ヒ１の変動Ｘは次のように
求めることかできる。As a result, according to the above equations (2>, (3), the printed resistance 3
The variation X in resistance 1 of the parallel resistances a and 3b can be determined as follows.
Ｒ８士Ｘ＝Ｒ＋Ｘ
ＲＡ
＝ （ｒａ＋２△ｒ）ｒｂ／
（（ｒ８＋２△ｒ）＋ｒｂ）
−（２Ｒ＋２△ｒ）２Ｒ／
（４Ｒ＋２Δｒ）
ゆえに ２Ｒ（２Ｒ＋２△ｒ）
＝（Ｒ＋Ｘ＞（４Ｒ＋２△ｒ）
となり、従ってＸ＝Δｒ／（２Ｒ十Δｒ ’） ・（４
）となる。R8shi , therefore, X=Δr/(2R+Δr') ・(4
).
第３図はトリミング後の抵抗値の変動率をグラフで示す
図である。式（１）に示す如く、従来例におけるトリミ
ング後の抵抗値の変動は△ｒとなるので、第３図に曲線
（１）で示す如く変動率は大きくなる。これに対して、
式（４）に示す如く、本実施例におけるＩ−リミング後
の並列抵抗値の変 。FIG. 3 is a graph showing the fluctuation rate of the resistance value after trimming. As shown in equation (1), the variation in resistance value after trimming in the conventional example is Δr, so the variation rate becomes large as shown by curve (1) in FIG. On the contrary,
As shown in equation (4), the change in parallel resistance value after I-rimming in this example.
勅は
八 ｒ／（２Ｒ十 Δ ｒ ）
となるので、第３図に曲線（２）で示す如く変動率は小
さくできる。従って、トリミングの精度を高めることが
できる。Since the force is 8r/(2R+Δr), the rate of fluctuation can be made small as shown by curve (2) in FIG. Therefore, trimming accuracy can be improved.
本発明は上記実施例に限定されるものではなく、種・々
の変形が可能である。例えば、並列に形成される印刷抵
抗は３本以上であってもにり、また、それぞれ異なる抵
抗値であってもよい。さらに、基板上に平行に配設され
るものに限らず、一対の端子間に並列に形成されていれ
ばいかなる配置であってもよい。The present invention is not limited to the above embodiments, and various modifications are possible. For example, three or more printed resistors may be formed in parallel, and each resistor may have a different resistance value. Further, the arrangement is not limited to being arranged in parallel on the substrate, but any arrangement may be used as long as it is formed in parallel between a pair of terminals.
（発明の効果）
以上、詳細に説明したように本発明によれば、複数の印
刷抵抗によって電気抵抗を形成したので、トリミング後
の抵抗値のドリフ１〜を低く抑え、従って設定値に対し
て！ｉ′ｉ度よく制御された電気抵抗を有する混成集積
回路装置を得ることができる。(Effects of the Invention) As described above in detail, according to the present invention, the electrical resistance is formed by a plurality of printed resistors, so that the drift of the resistance value after trimming is suppressed to a low level, and therefore ! It is possible to obtain a hybrid integrated circuit device having electrical resistance that is well controlled in i'i degree.
また本発明によれば、一対の端子間に複数の印刷抵抗を
形成し、次いで少なくとも１つを残して他の印刷抵抗を
トリミングするようにしたので、電気抵抗の抵抗値の調
整精度を向上させ、従ってトリミングによる抵抗値の調
整を正確かつ容易に行なうことができる混成集積回路基
板にあける電気抵抗の形成方法が１昇られる。Further, according to the present invention, a plurality of printed resistors are formed between a pair of terminals, and then the other printed resistors are trimmed, leaving at least one, thereby improving the accuracy of adjusting the resistance value of the electrical resistor. Therefore, a method for forming an electrical resistor in a hybrid integrated circuit board that allows adjustment of the resistance value by trimming accurately and easily is improved.
第１図は本発明の一実施例による印刷抵抗の形成を説明
する平面図、第２図は第１図に示す印刷抵抗に対してト
リミングを行った後の平面図、第３図はトリミング後の
抵抗値を変動率を示す図、第４図は従来例による印刷抵
抗の形成を説明する平面図、第５図は第４図に示づ一印
刷抵抗にトリミングを行った後の平面図である。
１・・・基板、２・・・端子、３，３ａ、３ｂ・・・印
刷抵抗、４・・・切り込み部。
特Ｌｌ’Ｆ出願人 住友電気工業株式会社代理人弁理
士 長谷用 芳 樹■発明のｌ’ｌｌす）ｌ抵
抗の平面図
筒 １ ス
本発明のトリミングの説明図
第２図
第 ３ 図FIG. 1 is a plan view illustrating the formation of a printed resistor according to an embodiment of the present invention, FIG. 2 is a plan view after trimming the printed resistor shown in FIG. 1, and FIG. 3 is a plan view after trimming. Figure 4 is a plan view illustrating the formation of a printed resistor according to the conventional example, and Figure 5 is a plan view after trimming to one printed resistor as shown in Figure 4. be. DESCRIPTION OF SYMBOLS 1... Board, 2... Terminal, 3, 3a, 3b... Printed resistance, 4... Notch part. Special Ll'F Applicant: Yoshiki Hase, Patent Attorney, Sumitomo Electric Industries, Ltd.■ Invention: Planar diagram of resistor 1 Explanatory diagram of trimming of the present invention Figure 2 Figure 3
Claims (1)
配設してなる所定抵抗値の電気抵抗を有する混成集積回
路装置。 ２、基板上の少なくとも一対の端子間に、所定抵抗値の
電気抵抗を形成する混成集積回路基板における電気抵抗
の形成方法において、 前記一対の電極間に複数の印刷抵抗を並列に形成する第
１のステップと、 前記複数の印刷抵抗のうちの少なくとも１つを残して他
の印刷抵抗をトリミングする第２のステップと を備えることを特徴とする混成集積回路基板における電
気抵抗の形成方法。 ３、前記第１のステップで形成される複数の印刷抵抗は
抵抗値が互いに略同一である特許請求の範囲第２項記載
の混成集積回路基板における電気抵抗の形成方法。[Scope of Claims] 1. A hybrid integrated circuit device having an electrical resistance of a predetermined resistance value, which is formed by arranging a plurality of printed resistors in parallel between a pair of terminals on a substrate. 2. A method for forming an electric resistance in a hybrid integrated circuit board, which forms an electric resistance of a predetermined resistance value between at least one pair of terminals on the substrate, the first step comprising forming a plurality of printed resistors in parallel between the pair of electrodes. and a second step of trimming the other printed resistors while leaving at least one of the plurality of printed resistors. 3. The method of forming electrical resistance in a hybrid integrated circuit board according to claim 2, wherein the plurality of printed resistances formed in the first step have substantially the same resistance value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61208474A JPS6364353A (en) | 1986-09-04 | 1986-09-04 | Hybrid integrated circuit device and formation of electric resistance in hybrid integrated circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61208474A JPS6364353A (en) | 1986-09-04 | 1986-09-04 | Hybrid integrated circuit device and formation of electric resistance in hybrid integrated circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6364353A true JPS6364353A (en) | 1988-03-22 |
Family
ID=16556770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61208474A Pending JPS6364353A (en) | 1986-09-04 | 1986-09-04 | Hybrid integrated circuit device and formation of electric resistance in hybrid integrated circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6364353A (en) |
-
1986
- 1986-09-04 JP JP61208474A patent/JPS6364353A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20090002120A1 (en) | Electrically adjustable resistor | |
| US6100787A (en) | Multilayer ceramic package with low-variance embedded resistors | |
| US5198794A (en) | Trimmed resistor | |
| US6725436B2 (en) | Resistor circuit | |
| JPH01304705A (en) | Trimming of film resistor | |
| JPS6364353A (en) | Hybrid integrated circuit device and formation of electric resistance in hybrid integrated circuit substrate | |
| JPS62174902A (en) | Trimming of thick film resistance element | |
| KR100464130B1 (en) | Resistance value adjusting method | |
| JPH04209501A (en) | Substrate for semiconductor device | |
| JPH01302701A (en) | Printed resistor | |
| JPH05235279A (en) | Semiconductor integrated circuit device | |
| JPS6290901A (en) | Square chip resistor | |
| JPH0252406A (en) | Chip resistor | |
| JPS61229302A (en) | Parallel type resistor unit | |
| GB1583684A (en) | Electrical layer resistor and a method for its manufacture | |
| JP2006278810A (en) | Thin film temperature sensor and method for adjusting characteristics thereof | |
| JPH0239563A (en) | Variable resistor element | |
| JPH03268301A (en) | Multiresistor for trimming use | |
| JPH0350704A (en) | Resistor formation and correction thereof | |
| JPH01264202A (en) | Resistance device for hybrid integrated circuit | |
| JPS63219105A (en) | Method of adjusting resistance value of printed resistor | |
| JPH01143204A (en) | Variable resistor | |
| JPH0316194A (en) | Thick film printed board | |
| JPH02148801A (en) | 3-terminal type thick film resistor and trimming method therefor | |
| JPH0372601A (en) | Film resistor |