JPS6364091B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a code conversion circuit, and more particularly to an improvement in a code insertion circuit that converts parallel codes into serial codes and adds a 1-bit predetermined code.

(b) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional code insertion circuit in this type of code conversion circuit, and FIG. 2 is a diagram showing an example of the operation process of FIG. 1. In FIGS. 1 and 2, a parallel code s0 consisting of 5 bits A, B, C, D and E is set in a 5-stage shift register SFR and then shifted to the right in synchronization with the clock signal clk. One bit is sent in the direction,
Bit A is output from the rightmost stage, which is the output stage of the shift register SFR, in the first period of the clock signal clk, and in the second
Bit B is sent out in the same cycle, and bit E is sent out in the same manner in the fifth period, and is sent out as a serial code s1. The serial code s1 is transmitted to the gate G1 and the parity code generation circuit PG. The parity code generation circuit PG generates a 1-bit parity check code p based on a predetermined parity check rule for the transmitted serial code s1, and transmits it to the gate G2.
On the other hand, the counting circuit CNT counts the clock signal clk that increments the shift register SFR, outputs a control signal c1 with a logic value of 0 while counting the first to fifth periods, and outputs a control signal c1 with a logic value of 0 while counting the sixth period. A control signal c1 with a logic value of 1 is output and transmitted to gates G1 and G2. Therefore, during the first to fifth periods of the clock signal clk, the gate G1 is in a conductive state and the gate G2 is in a blocked state, and the serial code s1 sent from the rightmost stage of the shift register SFR is transmitted to the gates G1 and G2.
3, and during the sixth period, the gate G2
is in a conductive state, gate G1 is in a blocked state, and parity check code p sent from parity code generation circuit PG is outputted via gates G2 and G3. As a result, a serial code s2 with parity is sent from the gate G3, in which a 1-bit parity check code p is added next to bits A to E.

As is clear from the above explanation, in a conventional code insertion circuit, in order to add the parity check code p to the serial code s1 converted from the parallel code s0, it is necessary to provide gates G1 to G3. There was a risk that the economic efficiency of the project would be impaired.

(c) Object of the Invention The object of the present invention is to eliminate the drawbacks of the conventional code insertion circuit as described above, and add a predetermined code consisting of 1 bit to the converted serial code without impairing the economic efficiency of the code conversion circuit. It consists in adding.

(d) Structure of the Invention The object of the present invention is to provide a code conversion circuit that converts an N-bit parallel code into a serial code using a shift register that can shift in both left and right directions according to a mode designation signal. When counting N clock signals for incrementing the register, the counting circuit switches the mode designation signal being sent for only one period of the clock signal, and the serial code output from the shift register is counted to 1. and a parity code generation circuit that generates a bit parity check code, and after setting the parallel code in the shift register, the shift register is shifted in the direction specified by the mode designation signal in synchronization with the input clock signal. Each bit of the parallel code is sequentially sent out serially from the output stage of the code, and after the sending of N bits is completed, the parity check code is shifted in the opposite direction by the switched mode designation signal, and the parity check code is transferred to the shift register. This is achieved by adding the parity check code to the serial code and sending it out by setting it in the output stage.

(e) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 3 is a diagram showing a code insertion circuit according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of the operation process of FIG. 3. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 3, the code conversion circuit is composed of a shift register SFR' which can be switched between right feed and left feed by a mode designation signal, a counting circuit CNT, and a parity code generation circuit PG, and includes gates G1 to G3 (gates G1 to G3). Figure 1) has been removed. Shift register SFR′ is a counting circuit
When the mode designation signal c2 transmitted from the CNT is set to a logical value of 0, the clock advances one bit in the right direction in synchronization with the clock signal clk, and when the mode designation signal c2 is set to a logical value of 1. Then, the bit is incremented by one bit in the left direction in synchronization with the clock signal clk. In FIGS. 3 and 4, 5 bits A,
Parallel code S0 consisting of B, C, D and E
is set in shift register SFR'. counting circuit
CNT counts the clock signal clk that advances the shift register SFR', transmits the mode designation signal c2 set to a logic value of 0 to the shift register SFR' during the first to fifth periods, and in the sixth period During this period, a mode designation signal c2 set to a logical value of 1 is transmitted to the shift register SFR'. Therefore shift register
SFR' is the clock signal during the first to fifth periods.
The clock signal clk is incremented by one bit in the right direction in synchronization with clock signal clk, and from the rightmost output stage, bit A is output in the first period of the clock signal clk, bit B is generated in the second period, and in the same manner, bit E is input in the fifth period. are sequentially transmitted as a serial code s1. The serial code s1 is output and also transmitted to the parity code generation circuit PG. The parity code generation circuit PG creates a 1-bit parity check code p based on a predetermined parity check rule for the serial code s1 to be transmitted, and outputs it to the shift register.
It is transmitted to the rightmost stage of SFR′. In the sixth period, the mode designation signal c2 is set to a logical value of 1, so the shift register SFR' advances one step to the left, and shifts the parity check code p transmitted from the parity code generation circuit PG to the rightmost stage. It is set and transmitted following the serial code s1. Note that bit E, which was set at the rightmost stage in the fifth period, is also sent to the leftmost right stage. In the seventh period, the mode designation signal c2 is again set to the logic value 0, so the shift register SFR' steps to the right, and bit E is sent out from the output stage again. As a result, from the rightmost stage of the shift register SFR', bits A to E are transmitted in the first to fifth periods of the clock signal Hclk, parity check code p is transmitted in the sixth period,
A serial code with parity s2' in which bit E is sent out in the seventh period is output.

As is clear from the above description, according to the present embodiment, the shift register SFR' is shifted to the right in the first to fifth periods of the clock signal clk to shift bits A to E.
is sent out as a serial code s1, and in the sixth period, a parity check code p is sent out by leftward feeding, thereby a serial code with parity s2' is outputted, and gates G1 to G3 are not required as in FIG.

Note that FIGS. 3 and 4 are only one embodiment of the present invention, and for example, the advancing direction of the shift register SFR' is not limited to that shown, and the leftmost stage is the output stage. It is also possible to consider reversing it as such, but the effect of the present invention does not change even in such a case. In addition, the parallel code s0 is not limited to one composed of 5 bits, but can be a shift register.
Although it may be considered to convert a parallel signal composed of arbitrary bits by changing the number of stages of SFR', the effects of the present invention remain the same in either case. Furthermore, the code added to the serial code s1 is not limited to the parity check code p; for example, many other modifications such as a frame code may be considered, but the effects of the present invention do not change in any case.

(f) Effects of the Invention As described above, according to the present invention, it is possible to add a predetermined code consisting of 1 bit to a converted serial code without impairing the economic efficiency of the code conversion circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional code insertion circuit, FIG. 2 is a diagram showing an example of the operation process of FIG. 1,
FIG. 3 is a diagram showing a code insertion circuit according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of the operation process of FIG. 3. In the figure, c1 is a control signal, c2 is a mode designation signal, clk is a clock signal, CNT is a counting circuit,
G1 to G3 are gates, p is a parity check code,
PG is a parity code generation circuit, s0 is a parallel code,
s1 is a serial code, s2 and s2' are serial codes with parity, SFR and SFR' are shift registers,
shows.

Claims (1)

[Claims] 1. In a code conversion circuit that converts an N-bit (N is a positive integer) parallel code into a serial code using a shift register that can be shifted in both left and right directions according to a mode designation signal, the mode designation signal is sent out. a counting circuit that switches the mode designating signal being sent for only one cycle of the clock signal when counting N clock signals that increment the shift register;
a parity code generation circuit that counts the serial codes output from the shift register and generates a 1-bit parity check code; Each bit of the parallel code is serially transmitted from the output stage of the shift register while shifting in the direction specified by the mode designation signal, and after the transmission of N bits is completed, the mode designation signal is switched in the opposite direction. 2. A code insertion circuit characterized in that the parity check code is added to the serial code and transmitted by shifting the serial code and setting the parity check code in an output stage of the shift register.