JPS6363230A - Start pattern detector - Google Patents

Abstract

PURPOSE:To correctly detect a start pattern and to minimize a circuit size by responding only to a 1st output that a coincidence detection circuit detects after the output of a pattern reproduction means is judged to have the same pattern as that of reception data, and outputting said output. CONSTITUTION:The output PN of the pattern reproduction means 11 and the reception data R DATA are inputted to an exclusive OR circuit 17. In a judgement means 12, the output of the pattern reproduction means 11 coincides with the reception data R DATA and the output of the exclusive OR circuit 17 comes to zero. Then the output of a filter 24 drops to a voltage at a low level. A hysteresis comparator 25 compares said output, and outputs CONT=0 as a switching control signal. The result that detects coincidence is outputted from an output means 14, where the judgement means 12 judges that the output of the pattern reproduction means 11 and the reception data have the same pattern. After CONT=0 is attained, response is made only to the 1st output that the coincidence detection means 13 detects, and only at that time MATCH=1 is outputted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a start pattern detection device, particularly a start pattern detection device for detecting a start pattern when receiving a digital signal having a signal configuration in which an information signal follows. Regarding.

[Conventional technology]

In order to process the received information signal, it is necessary to detect the starting point, or star pattern, of the information signal. In this sense, the start pattern must be detected accurately without error. especially.

The more important the meaning of the information signal, the longer the start pattern is used to ensure accurate detection. However, the hardware configuration for this has become extremely large.

FIG. 3 shows a configuration diagram of an example of a conventional start/turn detection device, which is a circuit for detecting a start pattern from received data (RDATA). To simplify the explanation, let's use this as a start to mother turn.

'11001' with n = 5 bits is selected.

In this example, a detection output can be obtained even if there is an error of r = 1 bit as the detection tolerance, and the detection results are output multiple times to the HATCH terminal.

Next, the circuit of FIG. 3 will be explained in detail.

1 is a shift register with n=5 stages, and stores only 5 bits of received data (RDATA). AND dirt 2
.about.6 output 1 even if there is a single focus error 9 in the start pattern in the received data.

If any one of AND darts 2 to f outputs 1 in the case of 0Rr-door, MATCH=1 is output. Circuits 8, 9 are inverters and when the start pattern is stored into the register.

AND &'-) The inputs 2 to 6 are all set to 1.

The circuit shown in Figure 3 uses n =
This is a case of 5 bits, and it is easy to realize this level. However, in this circuit.

Even when RDATA is neither a start nor a turn, the false detection rate is extremely high. For example, even though no signal is being received, noise (
When receiving with an FM receiver, it becomes a noise state when not receiving. ) is input, what is the rate of detecting a 5-bit start pattern from completely random noise with a 1-bit tolerance?

Pd −1/2 +5X1/25=3/16,
It happens 3 times out of 16 bits. Therefore, even when no signal is being received, there is a very high probability that a start pattern included in noise will be detected and erroneous processing will be performed.

So, for example, if a start pattern or turn consists of n = 100 bits, and the error tolerance can be up to r = 3 bits, what is the probability of finding a start pattern in a noisy state?

Pd=l/2100+1ooC1/2100+,. . c.
7'2100+, . . C3/2' 00Th,. .

C3/2' 00==1.6X 10-5, so this risk is small. However, regarding the circuit configuration at this time, 97 manual AND f-t is used as the dart corresponding to ANI)y-)2 to 6 in FIG. . C,=16
As many as 1,700 are required, resulting in an extremely large circuit scale.

[Problem that the invention seeks to solve]

That is, in the conventional device, if the length n of the start pattern was increased so as not to erroneously detect a turn in the tester toe from the noise, the scale of nine circuits would be very small, and it was difficult to realize this.

[Means for solving problems]

The start pattern detection device of the present invention includes: a pattern reproducing means for reproducing a start pattern; an electronic switch for selecting one of the received data and the output of the glossy turn reproducing means and inputting the result to the pattern reproducing means; Determination means for determining whether the output of the output reproducing means and the received data have the same pattern, and when it is determined that they do not match, generates a control signal to cause the electronic switch to select the received data. and.

a coincidence detection means for performing an E-turn match on the reproduction pattern of the turn reproduction means; and a coincidence detection means for performing an E-turn match on the reproduction pattern of the pattern reproduction means, and after the determination means determines that the output of the pattern reproduction means and the received data are the same pattern. and an output means that outputs an output in response only to the first detection output of the output.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In this figure, a five-stage shift register 15 and an exclusive OR circuit 16 are used as the gloss turn reproduction means 11. The electronic switch 1o selects either the received data (RDATA) or the output of the pattern reproduction means 11 (PN).

In this example.

The electronic switch 10 outputs the mother turn regeneration means (PN)
When you select , the trap is a 5-stage P
N (Pseudo No1se) signal (period = 25
-1=31 pits).

A switching control signal (CONT) for the electronic switch 10 is output from the determining means 12. If the output (PN) of the pattern reproducing means 11 and the received signal (RDATA) match, the determining means 12 outputs 0 as a switching control signal (CONT), and the electronic switch 10 switches the pattern reproducing means 11 to 0. Control is performed to select the output (PN).

Next, the 9 determining means 12 will be explained. The output (PN) of the turn reproduction means 11 and the received data (RDATA) are input to an exclusive OR circuit 17. Exclusive OR circuit 17
outputs 0 if (PN) and (RDATA) match. The output of this circuit 17 is passed through a low-pass filter 24 consisting of a resistor (R4) 18 and a capacitor (C1) 19 to suppress variations. Here 1 time constant R4C4
is selected to be sufficiently large compared to the time width of 1 bit. The output of the low-pass filter 24 is further compared with the base voltage v0 by the steresis comparator 25.

A hysteresis characteristic is provided by positively feeding back the results of the comparison between the hysteresis comparator 25u and the comparison 123f through the resistor (R,) 21. Resistance (R2) 20u
The output of the comparator 23 is chosen to be a little high so as not to adversely affect the filter 24.

That is, in the second judgment means 12, if the output (PN) of the pattern reproduction means 11 and the received data (RDATA) match and the output of the exclusive OR circuit 17 becomes O, the output of the filter 24 also becomes a low voltage. The steresis comparator 25 compares this with C0NT as the switching control signal.
= Outputs 0.

Electronic switch 10. Pattern reproduction means 119 judgment means 1
The operation of step 2 can be explained as follows using the time chart of FIG. In the section where no signal is received, the reception output is in a noise state. In this section, received data (RD
Since ATA) is completely random, it does not necessarily match the output (PN) of the mother turn reproducing means 11, and therefore the output x17 of the exclusive OR circuit 17 changes irregularly.

Therefore, a voltage higher than the comparison base single voltage is generated at the output ``24'' of the low-pass filter 24, and this is compared by the hysteresis comparator 25 and is used as the switching control signal C0.
Outputs NT = 1. At this time, the electronic switch 10
selects the received data side under control from the determining means 12 and inputs it to the pattern reproducing means.

Next, as a start pattern, 5-stage PN and turn “00”
0110111010100001001011001
1111'' is received as an example, and its operation will be explained.

When receiving this pattern, if at least 5 bits or more are input to the register 15, the output of the reproducing means and the received data have the property of matching, so that x,7=O.

In that case, as shown in Figure 2.

The voltage at the output 24 of the low-pass filter 24 is low.

When the voltage falls below a certain voltage vc-ΔV (Δ■ is the width of the steresis), the hysteresis comparator 25 responds and outputs the switching control signal C0NT=0. electronic switch 1
0 selects the output (PN) of the pattern reproducing means 11 and generates a signal independently of the received data (RDATA).

-Here, furthermore, if (RDATA) and (PN) are the same mother turn, x17=O remains.

Therefore, since the output of the 1 determining means 12 remains C0NT=0, there is no switching 9 of the switch 10.

If there happens to be an error in the received data at the moment when the electronic switch 10 is switched while receiving the start/so-turn signal, the following will occur. At this time, since an incorrect pattern is input to the shift register 15, (RD
ATA) and (PN) cannot be the same pattern, x,
7 becomes an irregular signal. Therefore, low-pass filter x2
The output of 4 is again a high voltage Kl, which is compared with the hysteresis characteristic and the regulator 25 and output as the switching control signal C0N.
Output T = 1. Therefore, shift register 1 again
5 receives received data (RDATA). Therefore, once again, the received data (RDATA) and the pattern reproducing means 1 are
The determining means 12 checks whether the outputs (PN) of 1 match each other,
Finally, the electronic switch 10 turns /4' turn regeneration means 1
Even if output (PN) of 1 is selected, this operation is automatically repeated until the state in which (RDATA) and (PN) stably match continues.

Conversely, the electronic switch 10 outputs the output (P
Even if you select N), if (RDATA) and (PN) continue to match, the received data (RDATA) will be 5.
It can be considered that the start turn consists of the PN signal of the stage. At this time, even if there is an error in the received data (RDATA), no error will occur in the output (PN) of the turn reproducing means 11. Therefore, the contents of the mother turn reproducing means (each output Q, -Q5 of the register 15) ), if the coincidence detection means 13 performs coincidence detection.

Error-free detection is performed. In the example in Figure 1.

ANDe-) 13 is used as the coincidence detection means 13.

A match is determined when the contents of the shift register are all 1s. The number of inputs to the AND gate 13 may be equal to the number of stages of the shift register 15.

The result of the match detection is outputted through the output means 14.

In this output means 14, the second judgment stage means 12 determines that the output of the mother turn reproduction means 11 and the received data are the same turn, and the first output of the coincidence detection means 13 is performed after C0NT=0. It responds only to the detection output of 9, and outputs h'1ATcI (=1) only at this time.Something relatively similar to the PN pattern occurs in the information signal, and the output of the 9 judgment means 12 remains C0NT=1.
If it remains O, the coincidence detection means may respond and output 1 again.

That is, from this second time onwards, when the coincidence detection means 13 responds, the output means 14 is used so that the response is not mistakenly processed as the beginning of information.

To explain the above operation in more detail: 1 Judgment means 1
2, it is determined that the output of the -e turn reproducing means 11 and the received data do not have the same pattern, and therefore the state is C0NT=1.

The set-reset circuit 26 is reset and the output is 0. Also, at this time, the flip-flop 27 outputs a non-inverted output Q=0. The inverted output is 10,000=1. Next, it is assumed that the output of the pattern reproducing means 11 and the received data have the same pattern and C0NT=0. Therefore, when the output of the coincidence detection means 13 rises, the set reset circuit 26 rises to 1. At this time, the flip-flop 27
The inverted output of is operated by the clock CLK, and the time of one bit remains 10,000=1, and MATCH=1 is output through the AND gate 28.

One bit after the output of the set-reset circuit 26 becomes 1, the flip-flop circuit 27 outputs an inverted signal.
Since it becomes 0, from now on, as the output of the AND gate 28,
She is the mother of MATCH=0. C0NT as it is
'= If O continues, the output of the coincidence detection means 13 from the primary is 1.
, the output of the set-reset circuit 26 is
Therefore, the output means 14 does not respond (MATC
) (= Followed by O.

In the embodiment shown in Fig. 1, there are five stages of p
N) The case of 31 bits of e-turn was explained. For example, if the starting turn is very long.

Even if it is about 1000 bits, it is still a circuit scale.

This can be realized by increasing the number of stages of the register 15 to 10 without significantly changing one circuit.

As for the operation, the start pattern is played back in synchronization with the received data in the turn playback means 11, and the pattern playback means 11 performs coincidence detection, so it is not directly related to bit errors contained in the received data. Detection is performed without Therefore, detection errors are extremely rare.

In the explanation of FIG. 1, for the sake of clarity, the determination means 12 was explained in an analog manner using a filter 24 and a bisteresis comparator 25.

An UP//'Dow counter is used in place of the filter 24.

It is also possible to use a digital comparator instead of the bisteresis comparator 25 for processing.

In this case, 9 (for example, UP/1) as an OWN counter.

Set the cuff to go down when the count is up at x1.

〔Effect of the invention〕

As explained above, the start/turn detection device of the present invention is capable of detecting a start/turn without error for extremely long start turns or turns.
Moreover, the circuit scale for this purpose is of course very small compared to conventional devices, and the detection of the start turn is performed only once when the start pattern is being received, and from then on, the start turn is detected in the information signal. even if it contains something close to a turn.

There is no possibility that the turn match output will respond again in response to this observation.

Remaining days below

[Brief explanation of drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment according to the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. 1.
FIG. 3 is a diagram showing a circuit configuration of an example of a conventional start pattern detection device. In the figure, 10...electronic switch, 11...or turn regeneration means, 15...shift register, 16...
- Exclusive OR circuit, 12... Judgment means, 17... Exclusive OR circuit, 24... Low pass filter, 18...
·resistance. 19...Capacitor, 25...-Hysteresis comparator, 20.21...Resistor, 22...Volume,
23... Comparator, 13... Match detection means, 14...
・Output means. 26...Set reset circuit, 27...Flip-flop circuit, 28...AND circuit. Figure 3 LK

Claims (1)

[Claims] 1. Pattern reproducing means for reproducing a start pattern;
an electronic switch that selects either the received data or the output of the pattern reproducing means and inputs the result to the pattern reproducing means; and whether or not the output of the pattern reproducing means and the received data are the same pattern. Judging,
a determining means for generating a control signal to select the received data in the electronic switch when it is determined that there is a mismatch; a matching detecting means for pattern matching the reproduction pattern of the pattern reproducing means; output means for outputting only in response to the first detection output of the output of the coincidence detection means after the means determines that the output of the pattern reproduction means and the received data are the same pattern; A start pattern detection device comprising: 2. The start pattern detection device according to claim 1, wherein the start pattern is composed of a PN signal.