JPS6362420A - Parallel processing method for echo canceler - Google Patents

Abstract

PURPOSE:To suppress a signal even with a large echo delay by inputting a signal including an echo to an echo canceler of the 1st stage only so as to obtain a residual echo signal. CONSTITUTION:Echo cancellers 12, 13, 14 are connected in cascade, and a signal including an echo signal Yn is fed to the echo canceler 12 of the 1st stage and no signal is applied to the echo cancellers 13, 14 of the post-stage. The echo cancellers 12, 13, 14 are operated in parallel at the same time and the result of each operation is added by an adder circuit 15 to obtain the residual echo signal. Thus, the high speed processing is attained and a large echo delay is suppressed sufficiently by increasing the number of connections.

Description

[Detailed Description of the Invention] [Summary] In an echo canceller parallel processing method, at least two
A signal containing an echo is input to the first echo canceller among the echo cancellers, and the other echo cancellers perform processing without inputting this signal, and then add the processing results in an adder circuit. By determining the residual echo signal, even if the echo delay is large, it can be suppressed.

[Industrial application field]

The present invention relates to an echo canceller parallel processing method.

FIG. 3 shows an example of a configuration diagram of a conference system using an echo canceller.

As shown in the figure, the audio signal X from the other party is applied to the speaker 2 via the line 4, converted into an acoustic signal and sent out to the outside, but for example, due to reflection inside the conference room, it wraps around the microphone 3 and causes reverberation. The signal returns to the other party through the line 5 as a signal (hereinafter referred to as an echo signal) and interferes with the communication.

Therefore, the echo canceller 1 is provided to suppress such echo signals as much as possible.

The echo canceller l has a transmission characteristic that approximates the transmission characteristic of the part that generates an echo (hereinafter referred to as the echo path), and takes in the signal X from the other side and generates an approximate echo signal (
By generating an echo signal y (hereinafter referred to as a pseudo echo signal) and adding it with the opposite phase to the actual echo signal y, the echo signal is suppressed to some extent and an attenuated echo signal (hereinafter referred to as a residual echo signal) e Since the signal returns to the other party's side, the degree of communication interference is improved, but the echo canceller is required to suppress echo signals with a longer delay.

(Conventional technology) FIG. 4 shows a block diagram of the echo canceller.

As shown in the figure, the echo canceller includes a coefficient storage circuit 8 that stores coefficients hN-i corresponding to N impulse responses of the echo path, and a coefficient storage circuit 8 that stores coefficients hN-i corresponding to N impulse responses of the echo path, and a coefficient storage circuit 8 that stores coefficients hN-i corresponding to N impulse responses of the echo path
There is a received signal storage circuit 7 that stores 1, and a convolution calculation section 10 performs a convolution operation between the coefficients read from this storage circuit and the received signal Xr+-i, thereby creating an echo path (not shown). ) is the same as the echo signal yn generated by (hereinafter referred to as the echo signal yn)

yfi (referred to as a pseudo echo signal) is generated. Therefore, the echo signal can be suppressed by calculating yn-yfi using the adder 11.

On the other hand, the impulse response of the echo path is determined by the adaptive control unit 6 using the residual echo signal e7 during the call. The coefficient update calculation section 9 automatically calculates
That is, the echo signal is identified and suppressed.

Note that the echo canceller performs the above processing using the following equation.

・Coefficient update operation (w) hook-1) tli =h= ”Kn-I Hxl, -4-l
(11・Calculation of pseudo echo signal y,,゛ Δ N−1C town y,=Σh,・Xn−1(21 −〇・Calculation of residual echo signal e1 e11=Vn)′I,(31・Coefficient for update Calculation N-1.

The old signal Xn-N and the corresponding coefficient hN-1 are read from K, = αen/Σx++-4 (41, that is, the received signal storage circuit 7, the coefficient storage circuit 8, and clH), and the convolution calculation unit 10 After calculating -+Xn-N using the multiplication circuit (not shown) in
) l-1) An addition/subtraction circuit (not shown) in the military further adds h-1 and calculates the updated value (η) by calculating equation (1). Next, the multiplication circuit uses the updated h2-1 (
2) After calculating the formula for Xl-0-0, calculate (
1) Perform the coefficient update calculation of the equation. After repeating such calculations to obtain yn, further calculate (3) 2 to suppress the echo signal y7. Further, K is calculated after executing equation (3).

In other words, in the echo canceller, after obtaining y7 by alternately repeating the convolution operation and the coefficient update operation,
The echo signal yn is suppressed by calculating the equation.

Here, (2) the convolution operation is performed using the received signal x1-8 from the received signal storage circuit 7 and the coefficient storage circuit 8 and the coefficient B
Since a filter-like operation is performed using h, h is called a tap coefficient and N is called the number of taps.

It can be found using hi, that is, belief.

Also, a parameter K for updating coefficients. is calculated by the adaptive control unit 6.

Note that if the echo delay occurring in the echo path is large, the number of taps N must be set to around 1000 to 2000.
The amount of echo delay that can be suppressed by one echo canceller is limited by the number of taps corresponding to the storage capacity of the reception storage circuit and coefficient storage circuit.

For example, when converted to LSI, 500 taps/chip is about 6
Since an echo delay of 0 m5ec can be accommodated, three to four echo cancellers are required in the above case.

FIG. 5 is a block diagram of the conventional example, and FIG. 6 is an explanatory diagram of the operation of the conventional example. The operation shown in FIG. 5 will be explained below with reference to FIG.

As shown in FIG. 5, for example, the output side of the echo canceller 12 is connected to the input side of the echo canceller 13, the output side of the echo canceller 13 is connected to the input side of the echo canceller 140, and the residual echo signal e7 is output from the output side of the echo canceller 14. It is configured to take out the

Also, the echo canceller 12 uses the coefficients h0 to hN-1 and the received signal sequence as x, .
, 1- +ZN-11, echo canceller 14 is h Z
Using N values of N~h 3N-1 and Xn-2N~X7~(38-+) and using equations (1) to (4) above, the pseudo echo signal ynctz> *y11 (
1311yll (calculate +41.

Note that ynu□) is a pseudo echo signal of the echo canceller 12.

Then, the residual echo signal e, using the following equation.

seek. However, y7 is the input signal (echo signal)
.

:l'1% -y n (1z+ =e+5
(12+ (5)el
l(+2l-yn(+z)=enf13+'(61en
(11+ 3'n(1a+ =elI(Im)
(71 Note that (!ailZl indicates 87 of the echo canceller 12.

This method uses the efl calculated in the previous stage as shown in Figure 6.
Subtract ynusr from (12) ejlfl:l)
, and further subtract yn(+o to obtain e +s(+41
= 6, , so the echo canceller 12~
14, it is necessary to start the calculation with a slight time delay, and three types of calculation start signals are required, but the deviation of this control signal is caused by the data transfer time 1t and the calculation of equations (6) and (7). The decision must be made taking into consideration the timing of

[Problem that the invention seeks to solve]

However, in order to suppress large echo delays, it is necessary to increase the number m of connected echo cancellers (where 2m is a positive integer), but the value of m becomes large (as shown in Figure 6, 7 calculations are required). Therefore, if the echo delay is large, the echo signal may not be suppressed sufficiently or may not be suppressed sufficiently.

[Means for solving the problem] The above problem can be solved by providing at least two echo cancellers 12, 13, 14 and an adder circuit 15 that perform processing for canceling echo signals, as shown in FIG. , the echo signal is applied only to the first-stage echo canceller 12 among the two echo cancellers, and no echo signal is applied to the remaining echo cancellers 13 and 14; This problem is solved by the echo canceller parallel processing method of the present invention, which simultaneously performs parallel processing and adds the processing results in the adding circuit to suppress the echo signal.

[Effect]

In the present invention, at least two echo cancellers are connected via IF, and a signal containing an echo signal is applied to the first-stage echo canceller, but no echo signal is applied to the second-stage echo canceller. At least two echo cancellers are operated in parallel at the same time, and the results of each operation are added in an adder circuit to obtain the residual echo signal, which enables high-speed processing and increases the tangent Vt by several meters. Therefore, even when there is a large echo delay, the suppression is sufficiently performed.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operating state of FIG. Note that the same reference numerals indicate the same objects throughout the figures.

The operation shown in FIG. 1 will be explained below, taking as an example the case where three echo cancellers each having N taps are used as in the conventional example.

First, as described above, the echo canceller 2 calculates x, which is stored in the received signal storage circuit 121 in the calculation circuit.

Using N received signals from to X h-(N-0,
: Y n ++z, is added to the input echo signal y7 in the adder 125, and the residual echo signal e1<1□
)=3' n Y n t. , get.

Next, no input signal is applied to the echo canceller 3, but the received signal is calculated by calculating y□, 〉 from N values up to
3'+off is obtained.

Similarly, in the echo canceller 14, all(+4>
=0)'+14) is obtained.

These values are added by an adder circuit 15 to obtain residual echo signals e and l as shown below.

en =Yn (y?1(Iz+ +3'nt+
3+ 10yn (+a+) This calculation operation is performed as shown in FIG. 2, when the calculation start signal is echo canceller 12.13.
14 at the same time, the above calculations are performed simultaneously, and the obtained calculation results are simultaneously applied to the adder circuit 15 to obtain a residual echo signal.

In other words, since the calculation start timing is the same and the timing to obtain the residual echo signal is also the same, even if the number of connections increases, the allowable time for calculating the allocation of 7 becomes longer, and since the calculation results can be obtained at the same time, it is necessary to transfer them. There is no need to consider timing.

That is, even echo signals with a large delay can be sufficiently suppressed.

〔Effect of the invention〕

As explained in detail above, the present invention has the advantage of being able to adequately cope with echo signals with a large delay.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of Fig. 1, Fig. 3 is an example of a configuration diagram of a conference system using an echo canceller, and Fig. 4 is a block diagram of an echo canceller. , FIG. 5 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of the operation of FIG. 5. In the figure, 6 is an adaptive control section, 7 is a received signal storage circuit, 10 is a convolution operation section, 11 is an adder, 12, 13, 14 is an echo canceller, and 15 is an addition circuit.

Claims (1)

[Claims] At least two echo cancellers (12, 13, 14, . . . ) and an adder circuit (15) are provided that perform processing for canceling echo signals, and among the at least two echo cancellers, an adder circuit (15) is provided. An echo signal is applied only to the first-stage echo canceller (12), no echo signal is applied to the remaining echo cancellers (13, 14, etc.), and the at least two echo cancellers are processed in parallel at the same time, and the processing results are 1. A parallel processing method for an echo canceller, characterized in that echo signals are suppressed by adding them in the adding circuit.