JPS6362049A - Tracing circuit - Google Patents

Abstract

PURPOSE:To perform the debug with no increase of the trace capacity by storing the address of a read instruction (FPS read instruction) for a control information memory set in an execution mode of a trace-on instruction and the information read out by said read instruction. CONSTITUTION:When a trace-on instruction is stored in a microprogram instruction register MIR3, this instruction is decoded and a trace-on instruction circuit 14 is started to secure a trace enable state. When an FPS read instruction is stored in the MIR3, the reception of this instruction is stored in an instruction memory circuit 11. At the same time, the address value of an address register 2 is stored in an address memory circuit 10. A tracing circuit 13 writes the information on the circuit 10 and the information on a control information memory circuit 8 into a due position of a trace memory address control circuit 12 in the form of a single piece of information.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a trace circuit that stacks and records the trajectory of information indicating microprogram execution addresses and internal states in a microprogram control type processing device.

[Conventional technology]

Conventionally, the trace circuit of this type of processing device stops the execution of the microprogram and also stops tracing when an error occurs or when the microprogram address matches a predetermined address. The purpose was to trace and analyze the events before the event.

[Problem that the invention seeks to solve]

In the conventional trace circuit described above, since control information for which information is frequently written/read is not stored as trace information, the microprogram writes/reads information in the control information storage memory area and makes decisions based on that information. ,
If you repeatedly write/read the next information to the same location and then make a decision, you may not be able to tell what value the misjudged information was even if you look at the control information storage memo IJ 2 when the error stops, or you may have limited trace information. The disadvantage was that the necessary information could not be stored in the sled area.

[Means for solving problems]

The trace circuit of the present invention is a trace circuit that stacks and records the trajectory of information indicating the microprogram execution address and internal state in a microprogram control type processing device. A control information storage circuit that reads data from a storage memory and stores its contents; an address storage circuit that stores the address where the specific instruction is stored; and an instruction storage circuit that remembers that the specific instruction has been issued. The trace memory address control circuit that controls the trace memory address, the control information storage circuit, and the address storage circuit are unified by the trace-on command circuit that can enable/disable these stored circuits and the command storage circuit. The trace memory circuit stores trace information as one piece of trace information.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

The drawing is a block diagram of one embodiment of the present invention.

1 is a control storage (hereinafter referred to as C8) circuit which stores a group of microprogram instructions 't-, and 2 is an address register (hereinafter referred to as MAR) that determines the sequence of the microprogram instructions. 3 is that MAR
Microprogram instruction register (hereinafter referred to as MIR) that stores the microprogram instruction at the location specified by
, 4 is an instruction decoding circuit for determining the operating code of the MIR, and 5 is a control information storage memory read instruction (hereinafter referred to as FPS read instruction) determined by the instruction decoding circuit. 6 is a control information storage memory circuit from which stored information is read by the FPS IJ-code instruction; 7
is an FPS address register (hereinafter referred to as FAR
), 8 is a control information storage circuit that stores the information read from the control information storage memory if the trace-on instruction is executed, and 9 is a control information storage circuit that stores the information read from the memory to be determined by the microprogram. 10 is an address storage circuit that stores the contents of MAR when the FPS read command is issued if the trace-on command is executed.

Reference numeral 11 indicates an instruction memory circuit that stores the fact that the FPS read instruction has been issued if a trace-on instruction is executed; 12 indicates a trace memory address control that controls the address of the race memory according to instructions from the instruction memory circuit; A circuit (hereinafter referred to as TAC) 13 is a trace memory circuit in which information in the address storage circuit and information in the control information circuit are written as one trace information in accordance with the writing position designation of the TAC. The trace-on instruction circuit 14 is a trace-on instruction circuit that specifies a state in which trace execution is possible, and extracts the microprogram code at the address specified by MAR2 from the C81, inputs the information to 1MlR3, and stores it. Next, the operation code portion of the microprogram code is judged by the instruction decoding circuit 4 and executed according to its contents.

When the trace-on command is stored in the MIR 3, the command is decoded and the trace-on command circuit is set to enable tracing. When the FPS read command is stored in the MIR3, the command is decoded and recognized by the FPS read command 5. First, the occurrence of this command is stored in the command storage circuit 11, and at the same time, this command is stored in the MAR2 taken out from the C81. The contents are stored in the address storage circuit 10 and are simultaneously indicated by the address of the FAR 7 output from the MIR 3. At the same time as the information in the control information storage memory 6 is read out, the information is stored in the control information storage circuit 8, whereby the FPS IJ-
Trace information is prepared using the information of the control information storage memory read by the code command and the address information of the microprogram.

On the other hand, by storing the information from the control information storage memory in the all-purpose register circuit 9, the flow (address) of the microprogram is changed and processed based on the information used for condition judgment in the microprogram. Therefore, when the instruction storage circuit 11 is stored as trace information, T
Add 1 address to ACl 2 to trace memory circuit 1
The trace information is written by specifying the 1 write position (address) to 3. However, when the trace-off command is stored in MI R3 and the command is decoded, the trace-on command circuit can be reset and the trace operation can be stopped.

Through these series of operations, the information in the control information storage memory can be traced in accordance with the trajectory of the microprogram.

〔Effect of the invention〕

As explained above, the present invention stores the address of the FPS read command when the trace-on command is executed and the information read by that command as t - 1 piece of trace information.D) Race memory capacity You can easily debug microprograms by tracing the necessary information without increasing the amount of information.

Ru.

Claims (1)

[Claims] In a trace circuit that stacks and records the locus of information indicating the microprogram execution address and internal state in a microprogram control system processing device, the microprogram reads out the control information storage memory in accordance with a specific command and stores its contents. a control information storage circuit for storing; an address storage circuit for storing the address where the specific instruction is stored; an instruction storage circuit for storing the fact that the specific instruction has been issued; and enabling/disabling of the storage circuit. a trace memory address control circuit that controls a trace memory address by the instruction storage circuit; and a trace memory circuit that stores information stored in the control information storage circuit and the address storage circuit as one trace information. and when the trace-on instruction is set and the specific instruction is issued, the address where the specific instruction was stored and the information read from the control information storage memory at that time are continuously stored as one trace information. A trace circuit characterized by: