JPS6362042A - Fault detecting circuit - Google Patents

Abstract

PURPOSE:To decrease the hardware quantity and to attain reduction of the cost with a fault detecting circuit by decreasing the number of error reporting lines. CONSTITUTION:The output data on registers 1 and 2 undergo the parity check through the corresponding parity check circuits 6 and 7 respectively and these parity check information are supplied to the corresponding error reporting circuits 8 and 9. The duplicated outputs of register control circuits 3 and 4 are compared with each other by an error check circuit 5 and the error information showing coincidence or discordance of this comparison is supplied in common to both circuits 8 and 9. The circuit 8 reports occurrence of an error when the circuit 6 detects an error or the circuit 5 decides discordance of outputs between circuits 3 and 4. While the circuit 9 reports occurrence of an error when the circuit 7 detects an error or the circuit 5 decides discordance of outputs between circuits 3 and 4.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure detection circuit, and more particularly to a failure detection circuit for a data register and a register control circuit that controls this register.

PRIOR ART A block diagram of such a conventional failure detection circuit is shown in FIG. There are control circuits 3 and 4, and both register control circuits 3
, 4 output the same control signal.

Therefore, instead of controlling registers 1 and 2 independently with each output of register control circuits 3 and 4 as in this example, both registers 1 and 2 may be controlled in common with the output of one register control circuit. . This duplicated register control circuit 3.4
The duplicated outputs are input to the error check circuit 5, where a comparison check is performed on these 100 outputs, making it possible to detect errors in the register control outputs.

A parity check circuit 6.7 is provided corresponding to each register 1.2 to perform error checking on each output of the register 1.2. Parity information is added to each data stored in registers 1 and 2 in advance, so each parity check circuit 6 and 7
The parity check information is generated by performing a parity check on the data.

In such conventional fault detection circuit systems, in addition to parity check information corresponding to the data stored in each register,
Furthermore, since the control output error information of the multiplexed register control circuit is also output independently, there is a drawback that the number of error reporting signals increases.

Purpose of the Invention Therefore, the present invention has been made to solve the drawbacks of the conventional ones, and has the following objectives and...
The object of the present invention is to provide a fault detection circuit that can reduce the number of error report signal lines while maintaining the same types of error reports as conventional ones.

A fault detection circuit according to the present invention includes a plurality of registers each storing data with parity, a register control circuit multiplexed to control the registers, and a register control circuit for controlling the registers. an error check circuit that compares and checks multiplexed outputs to detect errors, a plurality of parity check circuits that are provided corresponding to the registers and perform parity checks on data stored in the corresponding registers, and each corresponding to the parity check circuit. and a plurality of error reporting circuits having corresponding parity check information as one input and the output of the error check circuit as another input in common, and the error reporting circuit has a common input indicating an error. The present invention is characterized in that an error report signal is generated in all cases, and in other cases, the corresponding parity check information is derived.

1凰1 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals.

In this example as well, two registers 1.2 are provided, and parity information is added to each stored data in advance. These registers 1.2 should be controlled by II. This is the same as the conventional example.

The duplex outputs of the register control circuits 3 and 4 having a duplex configuration are compared and checked by an error check circuit 5 to generate error information. Furthermore, the parity check circuits 6 and 7 provided corresponding to each register 1 and 2 are connected to the corresponding register 1.
．． A parity check is performed on the stored data of No. 2 to generate parity check information, respectively.

Further, in the present invention, error reporting circuits 8.9 are provided corresponding to the parity check circuits 6.7, and one input of each error reporting circuit 8.9 is provided with a corresponding parity check circuit 6. Parity check information of .7 is applied. Error information from the error check circuit 5 is commonly applied to each other input of the error report circuit 8.9. These error reporting circuits 8.9 derive error reporting signals to all outputs when the common input error information indicates an error, and otherwise derive the corresponding parity check information. It is configured to do so.

The operation of the blocks in FIG. 1 will be explained below. Each output data of registers 1 and 2 is subjected to a parity check in corresponding parity check circuits 6 and 7, respectively, and this parity check information is input to a corresponding error reporting circuit 8.9. The duplicated outputs of the register control circuit 3.4 are compared in the error check circuit 5, and error information indicating whether they are the same or not is commonly applied to each error reporting circuit 8.9.

In the error reporting circuit 8, the parity check circuit 6
If an error is detected in the error check circuit 5, or if the outputs of the register control circuits 3 and 4 do not match in the error check circuit 5, an error is reported. Error reporting circuit 9
In this case, an error is reported when an error is detected in the parity check circuit 7 or when the outputs of the register control circuits 3 and 4 do not match in the error check circuit 5.

Therefore, if an error report occurs only in the error reporting circuit 8, it is determined that it is a register 1 parity error, and if an error report occurs only in the error reporting circuit 9, it is determined that it is a register 2 parity error. If an error report occurs in both error reporting circuits 8.9, it is determined that an error has occurred in the register control circuit 3.4.

By doing so, there is an advantage that the number of signal lines for error reporting can be reduced although the same error detection as the conventional method is possible.

Note that in the above embodiment, register 11. Although the explanation has been given for the case where the IJ control circuit is duplicated, it is similarly applicable to a case where the IJ control circuit is made triple or more, and the number of registers is not limited to the embodiment.

As described above, according to the present invention, there is an effect that it is possible to perform the same error reporting as the conventional method with fewer signal lines.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional fault detection circuit. Explanation of symbols of main parts 1.2...Register

Claims (1)

[Claims] A plurality of registers each storing data with parity, a register control circuit multiplexed to control the registers, and an error check circuit that compares and checks the multiplexed outputs of the register control circuit to detect errors. , a plurality of parity check circuits each provided corresponding to the register and performing a parity check on the data stored in the corresponding register; and a plurality of parity check circuits each provided corresponding to each of the parity check circuits each having corresponding parity check information as one input and detecting the error. It has a plurality of error reporting circuits that share the output of the check circuit as other inputs, and the error reporting circuits all generate an error reporting signal when the common input indicates an error, and the error reporting circuits generate error reporting signals for all other cases. A failure detection circuit, characterized in that the failure detection circuit derives the corresponding parity check information when the parity check occurs.