JPS6361972A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To economically conduct a burn-in tests by turning on and off a terminal bias means which biases some or all of terminals to an optional logic level under external control. CONSTITUTION:PMOS Transistors(TR) 1-4 are pull-up TRs which operate as the bias means for the respective terminals and a terminal 105 is a pull-up control terminal for turning on and off them. The terminal 105 is normally biased by a resistor 15 to an 'H' level and the TRs 1-4 are off. When an internal logic circuit 14 outputs an 'H' level signal as an input/output switching control signal 201, tri-state buffers(TSB) 11 and 12 turn on and when an 'L' level signal is outputted, high impedance is obtained and an input mode is entered. Further, when a burn-in test is taken, the application of the 'L' level signal to the terminal 105 turns on the TRs 1-4 and a TSB control signal 202 falls to the 'L' level regardless of the level of the signal 201 outputted by the circuit 14.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit constructed on a semiconductor substrate and provided with means for biasing each terminal of an input circuit, an output circuit, and an input/output circuit. Related to semiconductor integrated circuits.

[Conventional technology]

In recent years, as microcomputers and the like have become more highly integrated and highly functional, the number of terminals in semiconductor integrated circuits has also tended to increase. For example, microcomputers with built-in liquid crystal drive circuits for liquid crystal displays are being developed that have terminals of 100 pins or more.

In the manufacturing process of semiconductor integrated circuits that include this type of microcombination, full bias voltage is applied to the power supply and each terminal at an ambient temperature of approximately 100 to 150°C in order to eliminate initial defective products. Then, an acceleration test called a static burn-in test is performed.

In conventional semiconductor integrated circuits, fixed resistors corresponding to the number of IC sockets and terminals are mounted on the printed circuit board for the burn-in test, and during the burn-in test, one set of fixed resistors is connected to the IC socket via a predetermined fixed resistor. A bias voltage is applied to each terminal of the semiconductor integrated circuit. The fixed resistor is used to bias the terminals in order to limit the current against overcurrents that may occur during burn-in tests, and to prevent damage caused by external noise at the input terminals in MO8 semiconductor integrated circuits, etc. used for.

[Problem that the invention seeks to solve]

In the conventional semiconductor integrated circuit described above, the number of terminals is 1.
If the number of bins exceeds 00, the terminal spacing becomes narrow, making it difficult to mount the bias resistors corresponding to the number of terminals on a printed circuit board for burn-in testing, and causing the printed circuit board to expand. There are drawbacks. Furthermore, as the number of terminals increases, the number of bias resistors also increases, leading to an increase in cost.

[Means for solving problems]

A semiconductor integrated circuit of the present invention includes a plurality of input, output, and input/output terminals, and includes terminal bias means for biasing some or all of the terminals to an arbitrary logic level; It is fully equipped with a control terminal for externally controlling the "on/off" operation of the bias means.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a main part of a first embodiment of the present invention, and is an example of application to a semiconductor integrated circuit constituted by two MOS transistors. As shown in FIG. 1, this embodiment uses PMO8 (P-channel MOS)
) An input circuit 16 including transistors 1-2 and inverters 5-6, an input/output circuit 17 including PMOS transistors 3-4, inverters 7-8, and tri-state buffers 711-12, and an output including inverters 9-10. circuit 18, AND circuit 13, and internal logic circuit 14
and a resistor 15.

In FIG. 1, PMOS transistors 1 to 4 are pull-up transistors that act as a biasing means for each terminal, which is a feature of the present invention, and a terminal 105 is a pull-up transistor for each pull-up transistor, which is also a feature of the present invention. This is a pull-up control terminal for "on/off" control.

In the normal state where no external signal is input, the terminal 105 is biased to a positive logic level (hereinafter abbreviated as @H'' level) by a resistor 15 configured inside the semiconductor device, and the PMOs 81 to 4 The pull-up transistor containing is in the "off" state.
A predetermined voltage +VDD is supplied from the terminal 108.

In the above state, when the internal logic circuit 14 outputs an @H'' level signal as the input/output switching control signal 201, the AND circuit 13 outputs a 1H'' level signal as the tristate buffer 7 control signal 202. ,
It is sent to tri-state buffers 11 and 12. The tri-state buffers 711 and 12 are turned on in response to the input of the tri-state buffer ft1lJ control signal 202 at the ``H'' level, and the signals of the corresponding internal logic circuits 14 are sent to the terminal 103. and output to 104. Furthermore, when a negative logic level (hereinafter abbreviated as "L" level) level signal is output as the input/output switching control signal 201 output from the internal logic circuit 14, the tri-state buffer control signal 202 is also
When the level is "L", the tristate buffers 11 and 12 become high impedance and change to input mode. At this point, signals applied from the outside through terminals 103 and 104f in the input/output circuit 17 are applied to the internal logic circuit 1 via inverters 7 and 8.
4 and is processed.

The above description of the operation is an explanation of the normal operation of a semiconductor integrated circuit.
A case where an "L" level signal is externally applied to the pull-up control terminal covered by 5 will be explained.

During the burn-in test, when an "L" level signal is applied to the terminal 105 via a predetermined printed circuit board terminal, the PMOs 81 to 4 are turned on. On the other hand, since the ''L'mL'm level signal is applied from the terminal 105, the tri-state buffer control signal 4202 is When the level signal is "L" level, the tri-state buffers 11 and 12 have high impedance. Therefore, when no external signals are applied to the multi-terminals 101, 102, 103 and 103, the inverter 5 ~8 to 1H”
A level level signal is applied, and each logic level at the internal logic circuit 14 and the output terminals including terminals 106 and 107 is determined in response to the input of this H'' level signal.

The above description is based on a so-called static burn-in test conducted under ambient temperature conditions of approximately 100-150°C.
This is an explanation of the operation at terminals 101 and 102.
, 103 and 104, a dynamic burn-in test can also be performed by externally applying a time-varying signal to them.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing the main parts of a second embodiment of the present invention. As shown in FIG. 2, in this embodiment, PMO
8) Transistors 19-20 and inverters 25-26
t-input circuit 37 including PMOS) transistor 21
-22, input/output circuit 38 including inverters 27-28 and tri-state buffers 32-33, inverters 30-31 and PMO8) transistors 23-24
an output circuit 39 including an inverter 29, an OR circuit 3
4, a resistor 35, and an internal logic circuit 35.

In FIG. 2, PMO8) transistors 23 to 24 as pull-up transistors are added to the output circuit 39, and a level signal input from the terminal 115 as a pull-up control terminal and an output from the internal logic circuit 36 are shown. The main difference from the first embodiment is that an inverter 29 and an OR circuit 34 are connected as circuits corresponding to the input/output switching control signal 201.

This second embodiment considers using a PMOS transistor that acts as a pull-up transistor as a load resistor of an output buffer during a burn-in test. Terminal 115 as a pull-up control terminal is 1H"
biased to the level, PMO8) transistors 19-2
Normal operation when 4 is in the "off" state is:
This is the same as in the first embodiment described above.

During a burn-in test, when a 1L'' level signal is applied to the terminal 115, the PMOS transistors 19 to
24 is turned on and pulled up to the 1H" level, and the OR circuit 34 outputs an "H" level regardless of the level of the input/output switching control signal 201 output from the internal logic circuit 36. The level signal is output as the tri-state buffer control signal 202, and the tri-state buffers 32 to 33 enter the output state.At this point, the input/output circuit 38'J? Tri-state buffers 32-33 and inverters 30-3, respectively
It acts as a load resistor for each buffer including 31. Therefore, when an "L" level signal is output from each of the buffers, a current can flow to each buffer through the corresponding pull-up transistor. Of course, it is possible to perform a static burn-in test, but during the burn-in test, the terminal 115K"L"
By applying a signal whose logic level changes over time to terminals 109 and 110, dynamic burn-in tests can be effectively performed with load resistors connected to terminals 111 to 114. be able to.

In the second embodiment shown in FIG. 2, during the burn-in test, the PMO8) range δ ranges 21 to 22 in the input/output circuit 38 are used as load resistances of the tristate buffers 32 to 33 that act as output buffers. However, as in the case of the first embodiment shown in FIG. 1, it is of course possible to use the output of the AND circuit 13 as a control input to the tri-state buffers 32-33. In this case, a static burn-in test and a dynamic burn-in test can be performed using the terminals 109 to 112 as input terminals.

In the above explanation, the input/output systems in the input circuit, input/output circuit, and output circuit are each divided into two types.
Although we have explained the operation in the case of 4 systems or 8 systems, in general, micro combinators etc.
Generally, the systems are configured as a pair, and it goes without saying that the present invention can be effectively applied even in such a case.

〔Effect of the invention〕

As explained above, the present invention can be applied to semiconductor integrated circuits with a large number of input/output terminals, and eliminates the need for bias means, which has conventionally been mounted on an external printed circuit board and caused problems during burn-in tests. This has the advantage that the difficulty in implementing the bias means can be eliminated, and the burn-in test can be carried out economically.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of a first embodiment of the invention, and FIG. 2 is a block diagram showing the main parts of a twentieth embodiment of the invention. In the figure, 1 to 4, 19 to 24...PMOS
Transistor, 5-10. 25-31...Inverter, 11-12. 32-33... Tri-state buffer, 13...AND circuit, 14.
36...Internal logic circuit, 15.35...
・Resistor, 16°37...Input circuit, 17,3
8...Input/output circuit, 18.39...
・Output circuit. Agent Patent Attorney Uchihara 8--'日:'. f6- λ power circuit each 17- Input/output port 18- Output circuit Fig. 1 3q- Output circuit Fig. 2

Claims (1)

[Claims] In a semiconductor integrated circuit having a plurality of input, output, and input/output terminals, terminal bias means biases some or all of the terminals to an arbitrary logic level; 1. A semiconductor integrated circuit comprising: a control terminal for externally controlling "off".