JPS61163717A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To execute a test without deteriorating the performance of an integrated circuit by providing an output control transistor for controlling an output of an emitter coupling logical circuit. CONSTITUTION:When executing an in-circuit test, 'H', and the same voltage as a base voltage applied to a constant-current source TR13 are applied to a control signal input terminal 17 and a driving signal terminal 18, respectively. In this case, even if an 'H' signal is applied to a logical input terminal of the base of an input TR11, a potential difference between the base and the emitter of the TR11 becomes smaller than that of output control TRs 14, 15, and the TR11 does not become on. In the same way, a reference TR12 does not become on either. Also, even in a circuit of the TR13, an operation is switched to that by a constant-current source TR16 for the time of a test. Accordingly, at the time of a test, the TRs 11, 12, 13 and 9, 10 for constituting the logical circuit concerned are all set to an off-state, and a relation to other connected logical circuit is detached.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device configured using an emitter-coupled logic circuit, and in particular to a semiconductor integrated circuit device configured to allow testing without deteriorating the performance of the integrated circuit. The present invention relates to integrated circuit devices.

[Conventional technology]

Testing of printed circuit boards in integrated circuit devices configured using semiconductor integrated circuits includes in-circuit testing, which tests individual mounted components and combined components in small units, and testing of the circuit configuration of the entire printed circuit board. Another type of test is a function test in which a test is performed by supplying data from an input/output connector on a printed circuit board. As the scale of the circuits that make up the equipment increases, it becomes extremely difficult to create data patterns for performing functional tests with a failure detection rate of IOOO%.

In order to improve testability, in-circuit testing involves connecting input terminals of individual electronic components such as LSIs (Large-Scale Integrated Circuits) and ICs (Integrated Circuits) on the mounted printed circuit board to the test terminals of external test equipment. Observe the data at each output terminal by giving data directly from the . At this time, k, which gives arbitrary data to each LSI to be tested, is determined by the specific LSI to be tested in order to eliminate the influence of the outputs of other LSIs connected to the input terminals of the The logic level of the output of other LSIs connected to the input terminal must be set to @Low''.

Conventionally, in the case of LSIs composed of emitter-coupled logic (ECL) circuits, the following two methods are known for forcibly setting the output logic level to "Low" level using an external signal. .

The first method is the backdrive method, and as shown in Figure 1, the logic level of the output of the other LSI (u?) connected to the input terminal of the LSI under test (Fa) is "Hl". , ph", and by forcing a current to flow to the test terminal, the logic level thereof is set to Low".

The first method is to use the LS to be tested, as shown in Figure 3.
Other LSI (J2) connected to the input terminal of I (J/)
Insert the deterrent gate sterilization terminal (3) on the output side of the detergent gate (jl), and set the logic level to "Low" by controlling the deterrent gate sterilization terminal (3).
This method allows arbitrary test data to be given from the test terminal (33).

[Problem that the invention seeks to solve]

In the backdrive method shown in Figure 1.

There is a problem in that an excessive current flows, even temporarily, as the output current of another LSI connected to the input terminal of the LSI to be tested (corro), leading to element destruction and performance deterioration. That is, if this problem is explained in more detail using FIG. 1 and FIG. 5, it will be as follows. FIG. 1 is a diagram specifically showing the circuit of the output terminal of another LSI (large) connected to the input terminal of the LSI to be tested.

Here, the circuit is a known emitter-coupled logic circuit (IIh
) is an output transistor, (da 3) is a test terminal, and the output transistor (uA) causes an output current Iout to flow, thereby generating an output voltage Vout at the output terminal. This output voltage V out is equal to the voltage applied from the test terminal (D3), and an output current I out corresponding to this voltage value flows out from the output transistor (Hir6). The relationship between the output voltage V out and the output current I out of this output transistor is as shown in FIG. 3. In FIG. 3, (xi) is a characteristic curve corresponding to logic 1'/J of the emitter-coupled logic circuit, and (52) is a characteristic curve corresponding to logic "0". As can be seen from this characteristic curve, the test terminal (4I3) forces the logic level @H to the output terminal of the emitter logic circuit.
When a voltage v!! of 1ph'' or a voltage ML whose logic level is @Low'' is applied, an output current, current I out, having a value of I, to Is flows depending on the logic state of the output of the logic circuit. Among these, the value of output current II is the output allowable current value I
The value is several times larger than mar.

Stress caused by this excessive NRIf K causes element destruction and performance deterioration.

On the other hand, in the case of the method of providing a deterrent gate as shown in Fig. 3,
Although it does not have the problem of leading to element destruction and performance deterioration like the back drive method, in this case, a suppression gate is required for each output terminal of each logic circuit, and the number of elements used to package the integrated circuit increases significantly. As the number of circuits increases, a delay corresponding to an I gate is added to each logic circuit, resulting in a problem in that the processing speed of the entire one-circuit device decreases.

The present invention has been made to solve the above-mentioned problems, and relates to a semiconductor integrated logic circuit device configured using an emitter-coupled logic circuit.

An object of the present invention is to provide an integrated circuit device configured so that a test can be performed without deteriorating the performance of the integrated circuit device.

[Means for solving problems]

A semiconductor integrated circuit device constructed using the emitter-coupled logic circuit according to the present invention has the following characteristics in relation to the respective collectors of the human-powered transistor and the reference transistor of the emitter-coupled logic circuit, and the common emitter resistance of the input transistor and the reference transistor. Two output control transistors with collector and emitter connected are provided.

By applying a control signal to the base of this output control transistor, the complementary outputs of the emitter-coupled logic circuit are both set to a low level, and the emitter-coupled logic circuit connected to the input terminal of the last target logic circuit is partially connected to the semiconductor integrated circuit device. It is designed to be substantially separable from the

[For production]

In this invention, since an output control transistor is provided to control the output of the emitter-coupled logic circuit, this output control transistor forces the output of the logic circuit to reach the logic level by inputting a control signal, regardless of the operation of the logic circuit. The logic output connected to the input of the logic circuit under test can be set to the "0" state during an in-circuit test. Further, since this output control transistor is not provided as a special output inhibiting gate, it does not cause a delay in the operation of the logic circuit device, and may not cause stress to the integrated circuit.

[Embodiments of the invention]

Hereinafter, an embodiment of the present invention will be described with reference to FIG.

The fgt diagram is a circuit configuration diagram of an emitter-coupled logic circuit used to configure the integrated circuit device of the present invention.

In this Figure 1, (//) is an input transistor,
(l2) is a reference transistor, (/3) is a constant current source transistor, (lda>, (/r) is an output control transistor% (16) is a constant current source transistor for testing, (v), (to ) is the output transistor.

Although not shown, a plurality of input transistors (l/) are connected in parallel according to the number of logic input terminals. (l) is a output control transistor (ta)
, (is) is a common control signal input terminal, (11) is a drive signal terminal for driving the constant current source transistor (/6) for testing, (/?) is the input transistor C//
) and reference transistor (l2) common process ζ
ivy resistance.

(0) is the NOR logic output of the emitter-coupled logic circuit, (
(22) and (3) are the same (OR logic output, (22) and (3)
are power supply lines, respectively.

During normal operation, the output control transistor (LDA),
A "Low" level is applied to the control signal input terminal (17) of the (ts), a power supply line is applied to the drive signal terminal (/j) of the constant current source transistor (/A), and a power supply voltage is applied to the drive signal terminal (/j) of the constant current source transistor (/A). 'A voltage at the same level as Vmm is applied, and the transistors (/da>Air) and (i4) are turned off. In this case, when @H1ph" is applied to the pace logic input terminal of the input transistor (l/), the input transistor (l/) turns on and the reference transistor (12
) is off and NOR logic output (ko) is 'Low'
level, the OR logic output (col) becomes "Hlph" level and performs normal logic operation.

During in-circuit testing, the control signal input terminal (
/? ), set the “H1I?h” level to the drive signal terminal (/
f) k applies the same voltage as the base voltage applied to the constant current source transistors (7, 7) IC, respectively.

In this case, even if the logic input terminal IIc "aiph" level signal of the base of the input transistor (/l) is applied, the common emitter resistance c? )k The resulting potential difference makes the potential difference between the pace emitter of the input transistor (it) smaller than the potential difference between the pace emitter of the output control transistors (lda) and (ts), and the human power transistor (l/) It does not turn on.

Similarly, the reference transistor (/2) does not enter the MOON state and remains in the OFF state. Further, in the circuit of the constant current source transistor (/3), the operation is similarly switched to that of the constant current source transistor (/6) for testing. Therefore, in this case, only the output control transistors (tu) and (tr) and the constant current source transistor (/4) for testing are in the on state. Since the output transistor (?) #(/47) is of course in the off state in this case, this emitter-coupled logic circuit is essentially in the off state and the NOR logic output (λ0)
, OR#R outputs (cono) are both at the ``''L ov @ level. That is.

During in-circuit testing, a transistor (//) that constitutes a specific emitter-coupled logic circuit.

(l2), (/3), and (ri1.(to)) are all turned off to disconnect them from other connected emitter-coupled logic circuits.

In the emitter-coupled logic circuit shown in the diagrams Nao and Gi, in order to turn off all the transistors that make up the emitter-coupled logic circuit, the last constant current source transistor (
16), but since it is only necessary to turn off the transistors related to logic operation, the constant current source transistor fi (/A) for testing is omitted, and the constant current in the emitter-coupled logic gate □ path is omitted. The source transistor (iJ') may be used during testing.

〔Effect of the invention〕

As explained above, according to the present invention, in a semiconductor integrated circuit device configured using an emitter-coupled logic circuit, an output control transistor for controlling the output of the emitter-coupled logic circuit is provided, and the output control transistor is used to control the logic circuit. Regardless of the operation of the specific logic circuit, the output of the specific emitter-coupled logic circuit is forced to the logic level @Low'' by the control signal input, and the specific logic circuit is connected to the input of the logic circuit under test during in-circuit testing. The logic output of can be set to "O". Moreover, the means for setting the logic output of this particular logic circuit to "0" does not apply voltage stress to the semiconductor integrated circuit, nor does it apply gate delay, so it is possible to
It is possible to provide a semiconductor integrated circuit device that can perform in-circuit testing without deteriorating its performance.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of an emitter-coupled logic circuit used to construct an integrated circuit device of the present invention, and FIG. 1 is an explanatory diagram of a circuit testing method using a conventional backdrive method. Figure J is an explanatory diagram of a conventional circuit testing method using an inhibition gate, Figure V is a circuit configuration diagram of a conventional emitter-coupled logic circuit, and Figure 3 is a diagram of output characteristics of the emitter-coupled logic circuit. -, (?), (zo), output transistor, (//)...
Human-powered transistor, (is)...Reference Stra:/
Di,;
6)-〇 Constant current source transistor for testing, (+7)・
9 system @ signal input terminal, (1g) self-drive signal terminal, (/
9)...Common two pick resistance, (C□) aIINOR ceramic output, (At)...OR logic output, (C2), (C3)
...Power supply line, (CoA), (jz)...Test object L
f9 I. (koku), (ko2)...Other LSL, (koz>, (
Js). (tI3)...Test terminal, (JII door e suppression gate,
(+5)... Inhibition gate opening terminal, (1) Φ" fist output transistor, (51), (52)... Output characteristic curve. 9.10-111 output transistor + 1------- One λ power resistor 12-----Reference transistor +3----
-- Constant current source transistors 14, 15-. 1! Power supply transistor + 6 - - - Constant current source transistor for testing + 7 - - - - - -
------- Horse ■ is the word terminal + 9 - - - 1 common emitter fence 9 2 O - - - - NOR logic output 2 + - - - OR logic output 22.23 -'! H Gen Itaki] Mogi a Rei 2 figure 3 figure b figure 4 figure 5

Claims (3)

[Claims] (1) In a semiconductor integrated circuit device configured using an emitter-coupled logic circuit consisting of an input transistor, a reference transistor, and a constant current source transistor, the respective collectors of the input transistor and the reference transistor of the emitter-coupled logic circuit , two output control transistors each having a collector and an emitter connected are provided between the common emitter resistor of the input transistor and the reference transistor, and a control signal is applied to the base of the output control transistor to control the emitter-coupled logic circuit. An integrated circuit device characterized in that complementary outputs of both are set to a low level so that a portion of the emitter-coupled logic circuit can be substantially separated from the semiconductor integrated circuit device. (2) The integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is comprised of a plurality of emitter-coupled logic circuits. (3) In a plurality of emitter-coupled logic circuits constituting a semiconductor integrated circuit device, the output control transistor is provided only in a specific emitter-coupled logic circuit, and the complementary outputs of the emitter-coupled logic circuits are set to a low level so that the specific emitter-coupled logic circuit 3. The integrated circuit device according to claim 2, wherein only the logic circuit is separated from the semiconductor integrated circuit device.