JPH083518B2 - Array IC test method - Google Patents

Description

The present invention relates to an array IC test method for line-sequentially driving a display device such as an ELD, PDP, LCD or the like.

[Conventional technology]

In recent years, as display devices such as ELDs, PDPs, LCDs, etc. have become larger in area, a large number of driving transistors (as many as the number of electrode lines) are required for performing so-called line sequential driving. If these transistors are not integrated into an IC, the cost of the display device as a whole will not drop.
IC conversion is being promoted. In such an IC, for example, 32 or 64 driving transistors are arrayed in the final stage, and a control circuit for the driving transistors is built in.

When carrying out GO and NOGO tests for such ICs, it is necessary to monitor the output waveforms of multiple terminals, and therefore, a method of investing a large amount of man-hours is usually employed. In Figure 3,
The block diagram for demonstrating an example of the test method of the array IC used conventionally is shown. Further, FIG. 4 shows pulse waveforms applied and monitored during the test. The IC shown in FIG. 3 comprises a shift register 11 for converting serial data D _I into parallel, a latch circuit 12 for holding parallel data, and NAND gates 13, 13 'for controlling the operation of output transistors. And n transistors T _{1 to} T _n array for driving the display device. Connect the load resistor R in series with the drain portion Vo ₁ ~Vo _n of the transistors T ₁ through T _n, by monitoring by the monitor device 30 the waveform of each drain terminal of the IC GO, to carry out the NOGO test , The conventional test method. In this case, the shift register
Every time the 11 input data D _I are transferred, data of “1” is sequentially sent to the latch circuit, and the switching operation of the output transistors T _{1 to} T _n can be controlled by opening the NAND gates 13 and 13 ′ appropriately. ing. Input S _t of the NAND gate 13 'to "1", adding pulse G ₁ ~G _n of the applied pulses in phase to one input EN of the NAND gate 13 to the gate, the output transistor T ₁ through T _n when the switching operation, for each transfer period (T _H), EN pulse and the negative-phase pulse is generated in the drain portion Vo ₁ ~Vo _n of the output transistor T ₁ through T _n. Conventionally, the pulse generated in the drain section has to be sequentially monitored by the probe terminal for the monitor device 30 one by one, and it takes a lot of time just to observe all the drain terminals in one chip. Was. In other words, it is clear that it takes a considerable amount of time to inspect all 1 wafers.
Work efficiency is poor.

Although a method using an IC tester can be considered, it is said that an IC tester system that can observe multiple terminals at the same time is considerably expensive. In particular, it is said that the manufacture of a system that can handle a high voltage (100 V or more) cannot be easily realized in reality.

Therefore, the method of sequentially transferring the connecting portions of the probing terminals for monitoring and monitoring has been a method that can be realized at low cost, but as mentioned above, there is a problem that it takes too many man-hours. For example, when testing an array IC1 chip consisting of 64 transistor arrays, it is necessary to sequentially observe 64 output terminals. This is the IC
The test requires a considerable amount of time and man-hours, leading to higher IC costs.

The purpose of the present invention is to eliminate such conventional drawbacks,
An object of the present invention is to provide an array IC test method capable of testing an IC with only one monitor.

[Means for solving problems]

To achieve the above object, the present invention provides a serial / parallel data conversion circuit for converting a 1-bit input signal into n-bit parallel data, and an output of the serial / parallel data conversion circuit according to a first control signal. A holding circuit which is held or controlled to always hold "0", and in the ON state or the OFF state depending on the logical operation result of the output of the holding circuit and the second and third control signals. A method of testing an IC consisting of n output transistor arrays, the number of which is controlled, wherein the drain terminals of the n output transistor arrays logically ORed to a single load are monitored, When the holding circuit is in a state of holding the output of the serial / parallel data conversion circuit by the control signal of An inverted signal of the result of the logical operation with the output of the holding circuit is input to the gates of the n output transistor arrays, and at least one of the n output transistor arrays is in the ON state and all the transistors are turned on. The first control period in which the off-state is controlled to appear alternately, and the second control signal when the holding circuit is always holding "0" by the first control signal. Thus, the inverted signal of the logical operation result of the third control signal and the output of the holding circuit is input to the gates of the n output transistor arrays so that all of the n output transistor arrays are turned off. The second control signal when the holding circuit is always holding "0" by the second period to be controlled and the first control signal. By this, the test period becomes from the third period in which all of the n output transistor arrays are controlled to be in the ON state, and GO
-It is designed to perform a NOGO test.

[Principle and operation of the invention]

All the outputs of the transistors arranged in an array are logically connected and connected to a load, and the waveform of the connection terminal is monitored by a single probe. This makes it easy
GO-NOGO test can be performed. In this case, if input data that enables control of the output transistor by the input pulse of the control gate circuit is given only for the period required to transfer one shift register stage, only for the period required to transfer all shift register stages. A pulse having the same frequency as the control pulse supplied to the control circuit is obtained at the output terminal, and it is possible to check whether or not the logic circuit and the transistor function. Furthermore, if control pulses are applied to the latch circuit and the gate circuit, these elements can be tested simultaneously in real time. If such a method is used, since only one waveform monitor is required as a device required for the test, it becomes possible to perform the test in a short time with an inexpensive device.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram for explaining a method of testing an array IC according to a first embodiment of the present invention. Also,
2 (a) and 2 (b) show pulse waveforms applied and monitored in order to perform this test. 1 and 2 (a),
In (b), the same numbers or the same symbols as in FIGS. 3 and 4 represent the same components. In this embodiment, all the drain terminals of the output transistors T _{1 to} T _n of the array IC 10 are logically connected. The waveform of the connection terminal Vo is observed by the monitor device 30 by applying a resistance to this connection terminal or by providing a load 20 including a resistance and an output transistor and a transistor of a reverse conductivity type (connected in series to the resistance). When the latter load is used, a pulse is applied to the transistor so that it turns on when the output transistor turns off. In any case, the waveform to be monitored is only the Vo waveform, so it is sufficient to use one waveform monitor such as an oscilloscope. If necessary, the pulse for operating the logic circuit may be observed, but the number of observation terminals will be about 2 to 4 at most. The pulse waveforms to be supplied to the test circuit of the array IC having such a configuration are shown below. The circuit of the array IC 10 is configured so as to be able to drive the flat panel display device line-sequentially, basically, a shift register 11 for converting serial data to parallel, a latch circuit 12 for holding parallel data, Gate circuits 13 and 13 'for performing a switching operation according to data or an independent switching operation according to a control pulse (in the present embodiment, 1
As an example, a gate circuit including a two-stage NAND gate circuit is shown) and output transistors T _{1 to} T _n .
The input unit D _I of the array IC, provides data to be "1" only one transfer period T _H, to transfer the shift register portion of the n-stage clock pulse C _L. In this case, if the latch circuit is opened as shown in FIG. 2 (a) (the state in which the parallel-converted data is sent to the output of the latch circuit 12: LE =
"1"), appearing data "1" is sequentially switching instead notwithstanding et al to the output L ₁ ~L _n latch circuit 12 for each one transfer, will be output. In the system where this data “1” is output from the latch circuit
The NAND gate circuit 13 sends a pulse having a phase opposite to that of the control pulse supplied to the other input terminal EN to the NAND gate 13 'in the subsequent stage. By setting to "1" input S _t of FIG. 2 (a) as shown in the NAND gate 13 ', only the system output transistors of the output of the latch circuit is "1", the control pulse EN Outputs a reverse-phase switching pulse to the output terminal Vo. When the input S _t of the gate circuit 13 'is set to "1", the pulse of the output of the latch circuit is "0" to the gate of the output transistor of the system "0" is supplied, the outputs The transistor is turned off. The output transistors that perform the switching operation are sequentially switched for each transfer period T _H. During the period T _H after transferring the n-stage serial data, the final stage transistor T _n is switched. When the waveforms of the drain terminals Vo of the transistors T _{1 to} T _n operating in this way are monitored, it is observed as a pulse waveform in which the operation waveforms of the respective transistors are added together. That is, nT _H
The switching operation is performed only during the period of, and the pulse waveform set to the power supply potential V _D is obtained during the other periods.

If at least one of the output transistors is always in the ON state as the failure mode, the potential of Vo drops near the "0" level. In addition, even if a failure occurs in the logic circuit and a "1" level signal is supplied to the gate of the output transistor, the same state will occur. Conversely, if a "0" level signal is supplied to the gate of the output transistor, or if the output transistor is always off due to a malfunction, the output pulse is output only during the period corresponding to the switching operation period of the output transistor. A pulse waveform that does not occur is observed. Such abnormal operation, because it is observed in a state set to "1" input S _t of the input LE and the gate circuit 13 'of the latch circuit, the shift register 11, gate circuit
Operation test of the remaining two circuits of 13 and the output transistors T ₁ functional test of the through T _n is to have what is not.

However, the test pulse waveform shown in FIG.
In addition to LE and S _t , the latch circuit 12 and the gate circuit 13 'can be tested at the same time. That is, the output transistor is caused to perform the switching operation corresponding to the pulse applied to the input EN of the gate circuit 13 in the period of nT _H (T ₁ ) described above, but the latch circuit is operated in the next operation period T ₂ (= nT _H ). The output transistors T _{1 to} T _n are turned off by setting only the input LE of “0” to “0” level and holding the data “0”. By doing so, the potential of the output terminal Vo becomes the power supply potential V _D in the period of T ₂ . In this case, if the operation of the latch circuit is abnormal,
Will remain pulse in the period T ₁ is set to the potential of V _D through occurs or alternatively T _1, period T _2,. Also,
In the next operation period T ₃ (= nT _H ), the input S _{t of the} gate circuit 13 ′ is
Is set to “0”. In this way, the output transistor T ₁ does not depend on the input pulse EN and the input data D _I of the gate circuit 13.
~ T _n are turned on at the same time. By the way, this gate circuit
If 13 'is abnormal, the ON state is maintained or the OFF state is maintained during the period of T _{1 to} T ₃ . In this way, all elements (shift register
11, the latch circuit 12, it can test the functionality of the gate circuits 13, 13 'and the output transistor T ₁ ~T _n). Moreover,
The IC test can be performed in a single operation using a single monitor device (it is sufficient if there are about 1 to 4 channel plug terminals).

〔The invention's effect〕

As described above, according to the present invention, a monitor device having a small number of plug terminals is used, and the waveform of one terminal is simply observed without switching the monitor terminals. A functional operation test of an array IC (which performs switching operation) can be easily performed. Moreover, it is only necessary to provide a resistance or a transistor of reverse conductivity as an external component, and the test apparatus can be constructed at a very low cost. By using such a test method, the array IC can be tested in a short time, so that the number of test steps can be significantly reduced and the cost of the IC can be reduced. It is very effective in industry.

In the present invention, an IC composed of an N-channel transistor array is taken as an example for convenience, but an IC composed of a P-channel transistor array may be used. Also,
The operation period of T ₂ and T ₃ may be set to an arbitrary period of T _H or more instead of nT _H. Furthermore, although an example using a NAND gate for the gate circuit of the logic circuit was taken up, other NOR, OR, E
It may be composed of elements such as xclusive OR and AND. In this case, the states of the input data D _I , the inputs EN, S _t, etc. may be appropriately changed so that the functional operation of these gate circuits can be tested.

[Brief description of drawings]

FIG. 1 is a block diagram of a test device for explaining an array IC test method according to the present invention, and FIGS. 2A and 2B are used when the array IC test method according to the present invention is carried out. Operation pulse timing diagram, FIG. 3 is a configuration diagram of a test apparatus for explaining a conventional array IC test method, and FIG. 4 is an operation pulse timing diagram used when the conventional array IC test method is carried out. . In the figure, 10: array IC, 11: shift register, 12: latch circuit, 13,
13 ': NAND gate circuit, 20: load, 30: monitor device.

Claims (1)

[Claims] 1. A serial-parallel data conversion circuit for converting a 1-bit input signal into n-bit parallel data, and holding an output of the serial-parallel data conversion circuit by a first control signal, or always "0". And a holding circuit that is controlled so as to hold the output of the holding circuit and a logical operation result of the output of the holding circuit and the second and third control signals.
A method for testing an IC composed of a plurality of output transistor arrays, comprising monitoring the drain terminals of the n output transistor arrays logically connected to a single load, and the holding circuit according to the first control signal. Is in a state of holding the output of the serial / parallel data conversion circuit, the inversion signal of the logical operation result of the third control signal and the output of the holding circuit is generated by the second control signal by the n number of A first input is inputted to the gate of the output transistor array and is controlled so that at least one of the n output transistor arrays is in an on state and when all of the transistors are in an off state. And the second control signal when the holding circuit is always holding "0" by the period and the first control signal. An inverted signal of the logical operation result of the third control signal and the output of the holding circuit is input to the gates of the n output transistor arrays, and control is performed so that all of the n output transistor arrays are in the off state. And the second control signal causes the holding circuit to always hold "0" by the second control signal and the first control signal, all the n output transistor arrays are turned on. The test period of the array IC is controlled by the third period, and the GO-NOGO test is performed.