JPS6361802B2 - - Google Patents
Info
- Publication number
- JPS6361802B2 JPS6361802B2 JP58133902A JP13390283A JPS6361802B2 JP S6361802 B2 JPS6361802 B2 JP S6361802B2 JP 58133902 A JP58133902 A JP 58133902A JP 13390283 A JP13390283 A JP 13390283A JP S6361802 B2 JPS6361802 B2 JP S6361802B2
- Authority
- JP
- Japan
- Prior art keywords
- microwave
- thick film
- metallized
- upper metal
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P7/00—Resonators of the waveguide type
- H01P7/08—Strip line resonators
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Waveguides (AREA)
Description
【発明の詳細な説明】
この発明はセラミツク基板を用いたマイクロ波
混成集積回路に関し、特に三端子マイクロ波半導
体素子を厚膜コンデンサにより一電源で動作させ
るマイクロ波混成集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microwave hybrid integrated circuit using a ceramic substrate, and more particularly to a microwave hybrid integrated circuit in which a three-terminal microwave semiconductor element is operated by a single power supply using a thick film capacitor.
第1図a、第1図bおよび第1図cは従来のマ
イクロ波混成集積回路を示す平面図、そのA−
A′断面図、およびそのB−B′断面図である。同
図において、1はマイクロ波帯において低誘電損
失を有するセラミツクなどからなる誘電体基板、
2はマイクロ波伝送線路、3は低域通過フイルタ
型のドレイン電極バイアス線路、4は低域通過フ
イルタ型のゲート電極バイアス線路、5はメタラ
イズスルーホールにより接地されたソース接地電
極、6は金線などのワイヤにより各伝送線路に接
続される三端子マイクロ波半導体素子、7はマイ
クロ波帯において低誘電損失、高誘電率を有する
マイクロ波用チツプコンデンサ、8は抵抗値Rb
の厚膜抵抗もしくはチツプ抵抗などのバイアス抵
抗、9はメタライズスルーホールなどにより接地
された抵抗端接地電極、10は三端子マイクロ波
半導体素子6をマイクロ波伝送線路2およびマイ
クロ波用チツプコンデンサ7に接続される金線な
どのワイヤ、11はソース電極をバイアス抵抗8
を介して接地するソース電位電極、12は接地電
極、13はメタライズスルーホールである。 1a, 1b and 1c are plan views showing a conventional microwave hybrid integrated circuit;
They are an A' cross-sectional view and a B-B' cross-sectional view thereof. In the figure, 1 is a dielectric substrate made of ceramic or the like having low dielectric loss in the microwave band;
2 is a microwave transmission line, 3 is a low-pass filter type drain electrode bias line, 4 is a low-pass filter type gate electrode bias line, 5 is a source ground electrode grounded by a metallized through hole, and 6 is a gold wire. A three-terminal microwave semiconductor element connected to each transmission line by wires such as 7, a microwave chip capacitor with low dielectric loss and high dielectric constant in the microwave band, 8 a resistance value Rb
A bias resistor such as a thick film resistor or a chip resistor, 9 is a resistor end grounding electrode grounded by a metallized through hole, etc., 10 is a three-terminal microwave semiconductor device 6 connected to a microwave transmission line 2 and a microwave chip capacitor 7. A wire such as a gold wire to be connected, 11, connects the source electrode to a bias resistor 8
12 is a ground electrode, and 13 is a metallized through hole.
なお、第2図は第1図a〜第1図cの電気的等
価回路である。 Note that FIG. 2 is an electrical equivalent circuit of FIGS. 1a to 1c.
次に上記構成によるマイクロ波混成集積回路の
動作について説明する。まず、低域通過フイルタ
を構成するドレイン電極バイアス線路3およびゲ
ード電極バイアス線路4を通して、三端子マイク
ロ波半導体素子6に直流バイアスを印加すると、
増幅器として動作する。このとき、直流的にはソ
ース電位VSはドレイン・ソース間電流IDSとバイ
アス抵抗8の抵抗値Rbの積、VS=IDS×Rbだけ接
地電位より高くなり、ゲートバイアスを接地する
ことにより、ソース・ゲート間VGSにはVGS=−
VS=−IDS×Rbのバイアスが印加される。また、
マイクロ波的にはマイクロ波用チツプコンデンサ
7を通して接地される。このため、1電源ソース
接地マイクロ波増幅器として動作する。 Next, the operation of the microwave hybrid integrated circuit having the above configuration will be explained. First, when a DC bias is applied to the three-terminal microwave semiconductor device 6 through the drain electrode bias line 3 and gate electrode bias line 4 that constitute a low-pass filter,
Operates as an amplifier. At this time, in terms of direct current, the source potential V S is higher than the ground potential by the product of the drain-source current I DS and the resistance value Rb of the bias resistor 8, V S = I DS × Rb, and the gate bias is grounded. Therefore, the source-gate V GS is V GS = −
A bias of V S =−I DS ×Rb is applied. Also,
In terms of microwaves, it is grounded through a microwave chip capacitor 7. Therefore, it operates as a single-power source common-source microwave amplifier.
しかしながら、従来のマイクロ波混成集積回路
ではマイクロ波用チツプコンデンサの取り付けに
ハンダ付などの工程が必要であり、さらに電気的
接続に際し、金等のワイヤボンド工程が増加する
などの欠点があつた。 However, conventional microwave hybrid integrated circuits require processes such as soldering to attach microwave chip capacitors, and also have drawbacks such as the need for additional wire bonding processes for electrical connections.
したがつて、この発明の目的はチツプコンデン
サを実装せず、基板上にコンデンサ構造を設ける
ことにより、製造工程を簡略化することができる
マイクロ波混成集積回路を提供するものである。 Accordingly, an object of the present invention is to provide a microwave hybrid integrated circuit which can simplify the manufacturing process by providing a capacitor structure on a substrate without mounting a chip capacitor.
このような目的を達成するため、この発明はセ
ラミツク基板などの誘電体基板と、上部金属、絶
縁物、下部金属の三層から構成され、この下部金
属がメタライズスルーホールで接地されて上記誘
電体基板上に形成される厚膜コンデンサと、この
厚膜コンデンサの上部金属上にマウントされる三
端子マイクロ波半導体素子と、上記厚膜コンデン
サの上部金属と厚膜メタライズのバイアス抵抗用
端子とを接続する厚膜メタライズの線路とを備え
るものであり、以下実施例を用いて詳細に説明す
る。 In order to achieve such an object, the present invention consists of a dielectric substrate such as a ceramic substrate, and three layers: an upper metal, an insulator, and a lower metal, and the lower metal is grounded through a metallized through hole to connect the dielectric A thick film capacitor formed on a substrate, a three-terminal microwave semiconductor element mounted on the upper metal of the thick film capacitor, and a bias resistor terminal of the thick film metallization connected to the upper metal of the thick film capacitor. This will be described in detail below using examples.
第3図a、第3図bおよび第3図cはこの発明
に係るマイクロ波混成集積回路の一実施例を示す
平面図、そのC−C′断面図、およびそのD−D′断
面図である。同図において、14は低誘電損失を
有するセラミツクなどの絶縁体、15はコンデン
サ電極として働く上部金属、16はこの上部金属
15とバイアス抵抗8の一端を接続する線路であ
る。 3a, 3b, and 3c are a plan view, a cross-sectional view along the line C-C', and a cross-sectional view along the line D-D', showing an embodiment of the microwave hybrid integrated circuit according to the present invention. be. In the figure, 14 is an insulator such as ceramic having low dielectric loss, 15 is an upper metal serving as a capacitor electrode, and 16 is a line connecting this upper metal 15 and one end of the bias resistor 8.
なお、第4図は第3図a〜第3図cの電気的等
価回路を示す。 Incidentally, FIG. 4 shows an electrical equivalent circuit of FIGS. 3a to 3c.
次に、上記構成によるマイクロ波混成集積回路
の構成について説明する。まず、コンデンサの下
部金属として働くソース接地電極5の下部金属、
低誘電損失を有する絶縁体14およびコンデンサ
の上部電極として働く上部金属の三層から厚膜コ
ンデンサを形成することができるため、上述した
ように、1電源ソース接地マイクロ波増幅器とし
て動作することはもちろんである。このため、第
1図a〜第1図cに示すチツプコンデンサが不用
になり、製造工程を簡略化することができる。 Next, the configuration of the microwave hybrid integrated circuit having the above configuration will be explained. First, the lower metal of the source ground electrode 5, which serves as the lower metal of the capacitor,
Since a thick film capacitor can be formed from three layers of an insulator 14 with low dielectric loss and an upper metal serving as the upper electrode of the capacitor, it can of course operate as a single power source common microwave amplifier, as mentioned above. It is. Therefore, the chip capacitors shown in FIGS. 1a to 1c become unnecessary, and the manufacturing process can be simplified.
なお、上述の実施例では三端子マイクロ波半導
体素子として、電界効果トランジスタや接合型ト
ランジスタなど種々のトランジスタを用いること
ができることはもちろんである。 In the above-described embodiments, it is of course possible to use various transistors such as field effect transistors and junction transistors as the three-terminal microwave semiconductor device.
以上詳細に説明したように、この発明に係るマ
イクロ波混成集積回路によれば部品点数が減少
し、作業工程が減少するため、製造工程が簡略化
され、信頼性を向上することができる。また、厚
膜コンデンサ構造はセラミツク多層基板技術によ
り容易に作成することができるので実用性が高い
などの効果がある。 As described in detail above, according to the microwave hybrid integrated circuit according to the present invention, the number of parts and work steps are reduced, so that the manufacturing process can be simplified and reliability can be improved. Further, since the thick film capacitor structure can be easily produced using ceramic multilayer substrate technology, it has the advantage of being highly practical.
第1図a、第1図bおよび第1図cは従来のマ
イクロ波混成集積回路を示す平面図、そのA−
A′断面図およびそのB−B′断面図、第2図は第
1図a〜第1図cの電気的等価回路、第3図a、
第3図bおよび第3図cはこの発明に係るマイク
ロ波混成集積回路の一実施例を示す平面図、その
C−C′断面図、およびD−D′断面図、第4図は第
3図a〜第3図cの電気的等価回路である。
1……誘電体基板、2……マイクロ波伝送線
路、3……ドレイン電極バイアス線路、4……ゲ
ート電極バイアス線路、5……ソース接地電極、
6……三端子マイクロ波半導体素子、7……マイ
クロ波用チツプコンデンサ、8……バイアス抵
抗、9……抵抗端接地電極、10……ワイヤ、1
1……ソース電位電極、12……接地電極、13
……メタライズスルーホール、14……絶縁体、
15……上部金属、16……線路。なお、同一符
号は同一または相当部分を示す。
1a, 1b and 1c are plan views showing a conventional microwave hybrid integrated circuit;
A' sectional view and its B-B' sectional view, Figure 2 is the electrical equivalent circuit of Figures 1a to 1c, Figure 3a,
3b and 3c are a plan view showing an embodiment of the microwave hybrid integrated circuit according to the present invention, a cross-sectional view taken along the line C-C' and a cross-sectional view taken along the line D-D', and FIG. 3A to 3C are electrically equivalent circuits. DESCRIPTION OF SYMBOLS 1... Dielectric substrate, 2... Microwave transmission line, 3... Drain electrode bias line, 4... Gate electrode bias line, 5... Source grounded electrode,
6...Three-terminal microwave semiconductor element, 7...Microwave chip capacitor, 8...Bias resistor, 9...Resistance end ground electrode, 10...Wire, 1
1... Source potential electrode, 12... Ground electrode, 13
...Metallized through hole, 14...Insulator,
15...upper metal, 16...railway. Note that the same reference numerals indicate the same or equivalent parts.
Claims (1)
属、絶縁物、下部金属の三層から構成され、この
下部金属がメタライズスルーホールで接地されて
上記誘電体基板上に形成される厚膜コンデンサ
と、この厚膜コンデンサの上部金属上にマウント
される三端子マイクロ波半導体素子と、上記厚膜
コンデンサの上部金属と厚膜メタライズのバイア
ス抵抗用端子とを接続する厚膜メタライズの線路
とを備えたことを特徴とするマイクロ波混成集積
回路。1. A thick film capacitor composed of a dielectric substrate such as a ceramic substrate, and three layers: an upper metal, an insulator, and a lower metal, and the lower metal is grounded through a metallized through hole and formed on the dielectric substrate; A three-terminal microwave semiconductor element mounted on the upper metal of the thick film capacitor, and a thick film metallized line connecting the upper metal of the thick film capacitor and the thick film metallized bias resistance terminal. A microwave hybrid integrated circuit featuring:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58133902A JPS6024701A (en) | 1983-07-20 | 1983-07-20 | Microwave hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58133902A JPS6024701A (en) | 1983-07-20 | 1983-07-20 | Microwave hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6024701A JPS6024701A (en) | 1985-02-07 |
JPS6361802B2 true JPS6361802B2 (en) | 1988-11-30 |
Family
ID=15115768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58133902A Granted JPS6024701A (en) | 1983-07-20 | 1983-07-20 | Microwave hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6024701A (en) |
-
1983
- 1983-07-20 JP JP58133902A patent/JPS6024701A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6024701A (en) | 1985-02-07 |
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