JPS6361499A - Semiconductor memory device and its driving method - Google Patents

Abstract

PURPOSE:To suppress the increase in the cycle time of a static semiconductor memory device having an error correction circuit by comparing the contents of a first address buffer with a second address buffer making the output as an input and controlling the two sets of ports of a memory cell. CONSTITUTION:A two port memory matrix 13 is read and writted through respective row selection driving devices 12A, 12B by the row address buffer 11A and the row address buffer 11B making this output as an input. Accordingly, a rewriting by corrected data at the time of generating the error through the error correction circuit part 14, an input/output buffer 16 or the like is carried out in parallel to a reading. This is applied to a column address similarly. A time required for rewriting substantially after the correction of the error does not appear during the cycle. When the contents of the buffers 11A, 11B coincide, the driving by the 12A is stopped through a comparator 19, an activating circuit 21 or the like and trouble due to the address competition of both the ports is prevented. This is also applied to the column address.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory device, and more particularly to a static type semiconductor memory device incorporating an error self-correction circuit and a method for driving the same.

(Prior Art) In semiconductor memories, the problem of soft errors due to alpha particles and the like has become apparent as the semiconductor memory becomes smaller, and soft errors are expected to occur due to deterioration of operating margins due to lower voltages. As a means to solve such problems, a method has been proposed in which an error self-correction circuit that automatically detects and corrects generated soft errors within the memory chip is incorporated into the memory. Error self-correction methods include a multi-cell 1-bit method in which one bit of information is stored in multiple memory cells and a soft error occurring in one cell is masked, and a method that uses an error correction code. From the viewpoint of the additional circuit scale required for error correction, the latter method using error correction codes is considered to be the most promising method. For example, a memory incorporating an error correction circuit using codes is 1 by Mano et al.
983 International Solid State Circuits Conference
l 5olid 5tateCircuits Con
reference) “Submi” on p234-235 of the manuscript
cron VLSI Memory C1rcuits
A schematic diagram of the structure of a semiconductor device having an error self-correction circuit using such a conventionally proposed error correction code is shown in FIG.

In FIG. 3, row addresses (A, , A1...).

An) is latched and amplified by the row address buffer 41 and passes through the one row selection driver 42 to select one word line of the memory matrix 43. All or part of the information of the information cell and test cell read by the selected word line is amplified by the sense amplifier and then sent to the error correction circuit 4.
4 is input.

Further, the column addresses (B, , B1 . . . , Bm) are input to the memory matrix 43 and the error correction circuit section 44 through the column address buffer 45 and the column selection drive device 46 . The error correction circuit section 44 generates a correction signal using the inputted information cell information and test cell information, and compares and corrects the information to be read determined from the row address information and column address information. Then, this corrected information is output to the input/output buffer 48, and at the same time, the corrected information is rewritten into the information cell. In such a conventional example.

Since the target is a dynamic memory that requires rewriting after reading due to destructive reading, the cycle time delay due to the addition of an error correction circuit is only the delay due to the additional error correction circuit.

(Problems to be Solved by the Invention) When the prior art as described above is applied to a static type memory, a significant increase in cycle time becomes a problem. In general, static memory is non-destructive read memory, so there is no need to rewrite the read memory cells, so the delay caused by adding an error correction circuit to static memory is due to the added error correction. This is because it is the sum of the circuit delay and the time required to rewrite information that has undergone read error correction. Therefore, there is a high possibility that the addition of an error correction circuit will cause a significant deterioration in memory performance and will be unacceptable to users.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device having an error self-correction circuit which improves the above-mentioned drawbacks of the prior art and minimizes the increase in cycle time due to the addition of the error correction circuit.

(Means for Solving the Problems) A static semiconductor memory device having an error correction circuit using the code of the first invention of the present application is: A memory having two ports, a first port and a second port. a memory matrix consisting of cells; a first address buffer that receives external address information as input; an output of the address buffer as input, and selects a first port side of a group of memory cells of the memory matrix that corresponds to the input; a first selection driving device that receives the output of the first address buffer as an input; a second address buffer that receives the output of the address buffer as an input; and a memory cell group of the memory matrix that corresponds to the input; a second selection driving device for selecting a second port side of; a circuit for detecting a match between address information latched in the first address buffer and address information latched in the second address buffer; and;
and a starting circuit that starts the first selection drive device based on the output signal of the coincidence detection circuit.

Further, a method for driving a static half-body memory device having an error correction circuit using the code according to the second invention of the present application is as follows:
A memory matrix consisting of memory cells having two ports, a first port and a second port; A first address buffer that receives external address information as input; An output of the address buffer is input and corresponds to the input; a first selection driving device that selects a first port side of a memory cell group of the memory matrix; a second address buffer that receives the output of the first address buffer; and a second address buffer that receives the output of the address buffer; a second selection driver that selects a second port side of a group of memory cells of the memory matrix corresponding to the input; address information latched in the first address buffer; a circuit for detecting a match of address information latched in the address buffer of the second invention; and a starting circuit for starting the first selection drive device based on an output signal of the match detecting circuit. A method for driving a static type semiconductor memory device having an error correction circuit using: a read cycle that always operates on the first port side in response to an external information read request and an information write request to the semiconductor memory device; and a write cycle operating on the second port side; if the match detection circuit does not detect a match, the write cycle operating on the second port side and the next cycle are performed simultaneously. A read operation is performed on the first port side; if a match is detected by the match detection circuit, the first port side does not perform a read operation, and outputs the information to be written at the second port. It is characterized by

(Operation) The present invention has improved the problems in the prior art by the above-mentioned means.

In other words, if the conventional technology used in dynamic memory is applied directly to static memory, reading data and rewriting after error correction will be performed serially, This is because the delay due to the addition of an error correction circuit increases compared to the memory of the present invention.
By using a memory cell with two write-only ports and performing read and write in parallel,
The time required for rewriting after error correction is effectively hidden.

In addition, in the method of reading and writing simultaneously, a problem arises when the same memory cell is accessed from two ports, but a circuit is provided to compare the addresses of the two ports, and if the two addresses match, The solution was to output the information to be written as is without performing a read operation.

(Example) Hereinafter, the present invention will be described in more detail with reference to the drawings.

An embodiment of the second invention of the present application will also be described with reference to six diagrams showing a memory configuration in a typical embodiment of the first invention of the present application in FIG. In FIG. 1, the row address (Ao=Az-..., An) input from the outside is the first row address of the memory matrix 13 consisting of two-port memory cells.
is latched into the row address buffer IIA acting on the port side of the row address buffer IIA. The row address information latched in the row address buffer IIA passes through the row selection driver 12A acting on the first port side of the memory matrix 13 to select one word line on the first port side of the memory matrix 13. do. The information read from the memory cell by the selected word line is amplified by the sense amplifier, and then the column address (Bo.

B i t..., Bm), necessary information is input to the error correction circuit unit 14. Also, the column address (B.,
B1. ..., Bm) are input to the column selection drive device 16A that acts on the first port side through the column address buffer 15A that acts on the first port side, and are input to the first port side of the memory matrix 13. At the same time, it is also input to the error correction circuit section 14 through the code selection drive device 17. This is because once the necessary information has been input to the error correction circuit section 14, the work on the first port side has been completed.

The first port side is returned to the standby state, and the bit line on the first port side starts precharging.

At this time, the row address information (A6
v AI H...t A n ) are transferred to the row address buffer 11B acting on the second port side.

Also, a column address buffer 15 acting on the first port side
Column address information latched in A (B,, B,
. . , Bm) are transferred to the column address buffer 15B acting on the second port side.

The error correction circuit section 14 detects and corrects errors in the information to be read using the input read cell information and address information. Then, this error-corrected information is output to the input/output buffer 18, and at the same time, using the second port, a memory supported by the address information of the row address buffer ylB and column address buffer 15B transferred from the first port side is output. rewrite the cell, that is, the original memory cell that was read. On the other hand, on the first port side, the standby state is completed while the error correction circuit section 14 is operating, and the first read cycle is started. That is, the next row address information is latched into the row address buffer IIA on the first port side.

Next, the address information stored in the row address buffer IIB on the second port side and the address information stored in the row address buffer IIA on the first port side are input to the comparator 19. Similarly, regarding the column address, the column address information for the next cycle is latched into the column address buffer 15A on the first port side, and the address information in this column address buffer 15A and the column address information on the second port side are stored in the column address buffer 15B on the second port side. address information is input to the comparator 20. The outputs of the comparators 19 and 20 are input to the starting circuit 21, and when the outputs of the peripheral comparators both show a match, the starting circuit 21 controls the row selection driving device 12A and the column selection drive device 12A on the first port side. Sends a signal that does not operate the selection drive unit [16A].

If the output of at least one of the comparators indicates a mismatch, the activation circuit 21 activates the row selection drive device 1 on the first port side.
2A and a signal to activate the column selection drive device 16A. Therefore, in the latter case, the same operations as described above are repeated. In the former case, the first port side does not perform a read operation, and the second port side outputs the information to be written as it is, which is the same operation as described above.

The driving method which is an embodiment of the second invention of the present application described above is shown in a simplified block form as shown in FIG. In the case of the conventional technology, the period from reading on the first port side to precharging on the second port side is one cycle, and in the method of this embodiment, the period from reading on the first port side to output is an effective one cycle. cycle, resulting in a significant reduction in cycle time compared to the prior art. Furthermore, with this driving method, there is no concern about contention between reading on the first port side and writing on the second port side, and there is no problem in this respect as well.

(Effects of the Invention) As described above, according to the invention of the present application, a semiconductor memory device having an error self-correction circuit that does not significantly increase the cycle time and a method for driving the same can be obtained and are useful.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a typical embodiment of the first invention of the present application, and FIG. 2 is a diagram schematically showing a driving method as an embodiment of the second invention of the present application. be. Further, FIG. 3 is a block diagram showing the configuration of a half-quad memory device having a conventional error correction circuit. 11A, IIB, 41... row address buffer, 12
A, 2B, 42... Row selection drive device, 13°43.
...Memory matrix, 14.44...Error correction circuit section, 15A, 15B, 45...Column at 1 nos buffer, 16A, 16B, 46...Column selection drive device, 17
．． 47... Code selection drive device, 18,481 output buffer, 19.20... Comparator, 21... Start-up circuit, 22.29... Read on first port 1- side, 23.
30... 1st port side precharge, 24, 31...
・Output, 25.32...Error correction, 26.33...
・Write on the second port side, 27.34...Precharge on the second port side, 28...Address comparison. Agent Patent Attorney Shinsuke Honjo Figure 1ゝ---～---ノ

Claims (2)

[Claims] (1) In a static semiconductor memory device having an error correction circuit using codes: A memory matrix consisting of memory cells having two ports, a first port and a second port; External address information is input. a first address buffer; a first selection drive device which takes an output of the address buffer as an input and selects a first port side of a group of memory cells of the memory matrix corresponding to the input; the first address; a second address buffer that takes the output of the buffer as an input; a second selection drive that takes the output of the address buffer as an input and selects the second port side of the memory cell group of the memory matrix corresponding to the input; a circuit for detecting a match between the address information latched in the first address buffer and the address information latched in the second address buffer; 1. A semiconductor memory device comprising: a startup circuit that activates a selection drive device. (2) a memory matrix consisting of memory cells having two ports, a first port and a second port; a first address buffer that receives external address information as input; and a first address buffer that receives external address information as input; a first selection driving device that selects a first port side of a memory cell group of the memory matrix corresponding to an input; a second address buffer that receives an output of the first address buffer as an input; the address buffer a second selection drive device which receives the output of the input and selects a second port side of the memory cell group of the memory matrix corresponding to the input; and address information latched in the first address buffer; A code comprising: a circuit for detecting a match of address information latched in the second address buffer; and a starting circuit for starting the first selection drive device based on an output signal of the match detecting circuit. In a method for driving a static type semiconductor memory device having an error correction circuit: a read cycle that always operates on the first port side in response to an external information read request and an information write request to the semiconductor memory device;
Write cycles operated on the second port side are performed sequentially; if the coincidence detection circuit does not detect a match, the write cycles operated on the second port side are performed simultaneously with the next cycle. A read operation is performed on the first port side; if a match is detected by the match detection circuit, the first port side does not perform a read operation, and the second port side outputs the information to be written. A method for driving a semiconductor memory device, characterized in that: