JPS6360562B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current mirror circuit, and particularly to a current mirror circuit suitable for integrated circuits with low input voltage and high output voltage.

A conventional current mirror circuit of this type will be briefly described with reference to the drawings. FIGS. 1 and 2 are circuit diagrams showing first and second examples of conventional current mirror circuits, respectively. In Figure 1,
As is well known, the current mirror circuit 1 includes current mirror transistors Q _a1 , Q _a2 , Q _a3
and a current amplification factor correction transistor Q _a4 added to reduce errors caused by base currents of the transistors Q _a1 , Q _a2 , Q _a3 , and the transistors Q _a1 , Q _a2 , Q _a3 , the influence of the base current is 1/β4 (where β4 is the current amplification factor of transistor Q _a4 ). transistor here
The input current to the collector of Q _a1 is indicated by I _IN , and the output currents from the collectors of transistors Q _a2 and Q _a3 are indicated by I _OUT1 and I _OUT2 , respectively. However, in this current mirror circuit 1, transistors Q _a1 and Q _a3
The current transfer ratio (I _OUT1 /I _IN ,
I _OUT2 /I _IN ) deteriorates, so transistors Q _a2 ,
It is necessary to make each emitter resistance R _a2 and R _a3 of Qa ₃₁ a large resistance value. Furthermore, if the characteristics of transistors Q _a1 , Q _a2 , and Q _a3 match, the current transfer ratio is determined by R _a2 /R _a1 and R _a3 /R _a1 , respectively, so the resistors R _a2 ,
If the resistance value of R _a3 is increased, the resistance value of resistor R _a1 must also be increased. That is, this circuit had the disadvantage that the area of the chip would increase when integrated.

Next, FIG. 2 shows a current mirror circuit that improves the drawbacks of the first example, and the current mirror circuit 2 includes transistors Q _b1 , Q _a2 , Q a3 , and Q _a4 corresponding to the transistors Q a1 , Q a2 , Q _a3 , and Q _a4 in FIG. Q _b2 , Q _b3 , Q _b4 ,
In addition, buffer transistors Q _b5 and Q _b6 are provided at the respective outputs of transistors Q _b2 and Q _b3 , and output currents I _OUT1 and I _OUT2 are obtained from their collectors, thereby reducing the output voltage of transistors Q _b2 and Q _b3 . This is a circuit that reduces the early effect. Note that the transistor
Connect the buffer power supply V _BUF to the bases of Q _b5 and Q _b6 . However, in this current mirror circuit 2, since the buffer power supply V _BUF is fixed, when the input current becomes large, the transistors Q _b2 and Q _b3 become saturated, so that the input current range is limited.
In addition, since a buffer power supply V _BUF is required, the configuration becomes complicated and the power consumption increases to create the power supply.

It is an object of the present invention to eliminate the above-mentioned drawbacks by making the input current range of the current mirror transistor unaffected by the output voltage without narrowing it, and to improve it so as to reduce the error. The purpose of this invention is to provide a current mirror circuit suitable for

According to the present invention, first and second transistors of a first polarity, the bases of which are connected to each other and whose respective emitters are connected to a power supply through respective resistors; a third transistor of a first polarity connected to the collector and base of the transistor; and a third transistor of a second polarity whose base and collector are connected to the collector of the third transistor and whose emitter is connected to a reference potential point. a fourth transistor of a second polarity, the base of which is connected to the collector of the third transistor and the emitter of which is connected to the reference potential point; a sixth transistor of a second polarity connected to the base of the transistor, the power supply, and the collector of the fifth transistor; the base is connected to the emitter of the sixth transistor and the emitter is connected to the second transistor and a seventh transistor of a first polarity connected to the collector of the current mirror circuit, wherein the collector of the first transistor is an input and the collector of the seventh transistor is an output. and the seventh transistor is a Darlington transistor, and a current mirror circuit is obtained, characterized in that the seventh transistor is a Darlington transistor, and a diode is inserted and connected in the forward direction between the emitter of the sixth transistor and the base of the Darlington transistor. It will be done.

Next, the present invention will be explained with reference to FIGS. 3 and 4.

3 and 4 are circuit diagrams of two-output current mirror circuits showing first and second embodiments of the current mirror circuit of the present invention, respectively. In Fig. 3, in the current mirror circuit 3, a current mirror transistor Q ₁ which supplies an input current I _IN to the collector
has its emitter connected to the power supply V _CC via a current mirror resistor R ₁ , and its base connected to the bases of current mirror transistor Q ₂ and current mirror transistor Q ₃ . The emitters of the transistors Q ₂ and Q ₃ are connected to the power supply V _CC through current mirror resistors R ₂ and R ₃ , respectively. and said transistor
The emitter of the current amplification factor correction transistor _Q4 whose base is connected to the collector of _Q1 is connected to the bases of the transistors _Q1 , _Q2 , _Q3 , and the collector is connected to the base of the current direction reversal transistor _Q5 ,
Collector and current direction reversal transistor Q ₆
connected to the base of The collector of the transistor Q ₆ is a buffer transistor connected in cascade to the emitter of the level shift transistor Q ₇ and the transistors Q ₂ and Q ₃ .
connected to the bases of Q ₈ , Q ₉ and the transistors Q ₅ ,
The emitter of Q ₆ is connected to the reference potential point (earth). The base of the transistor _Q7 is connected to the bases of the transistors _Q1 , _Q2 , _Q3 , and the collector is connected to the power supply _VCC . the transistor
The output currents of Q ₂ and Q ₃ are respectively
Output currents I _OUT1 and I _OUT2 are generated via Q ₈ and Q ₉ . Therefore, such a current mirror circuit follows the input current I _IN (follows the base voltages of the current mirror transistors Q ₁ , Q ₂ , Q ₃ ) and changes the base voltages of the buffer transistors Q ₈ and Q ₉ . is determined, the Early effect of the transistor can be reduced without narrowing the input current range.

Next, the current mirror circuit 4 shown in FIG. 4 replaces the buffer transistors Q ₈ and Q ₉ in FIG.
1.42, the transistor Q ₈ ,
In addition to reducing the influence of the current amplification factor of _Q9 , the level shifting diode _D1 is inserted and connected in the forward direction between the emitter of the level shifting transistor _Q7 and the bases of the Darlington transistors 41 and 42. This prevents the current mirror transistors Q ₂ and Q ₃ from becoming saturated. That is, the Darlington transistor 41 consists of buffer transistors _Q8 and _Q10 , the emitter of the transistor _Q8 is connected to the collector of the current mirror transistor Q2, and the base thereof is connected to the collector of the current mirror transistor _Q2 .
The collector is connected to the emitter and collector of the transistor _Q10 , respectively, and the base of the transistor _Q10 is connected to the diode _D1 , and the output current _IOUT1 is output from the collector. Similarly, the Darlington transistor 42 consists of transistors _Q9 and _Q11 , the base of the transistor _Q11 is connected to the base of the transistor _Q10 , and the output current is supplied from the collector of the transistor _Q11 .
I Output _OUT2 .

As a result of actual measurements for the second embodiment, the resistance values of the current mirror resistors R ₁ , R ₂ , and R ₃ were each 2KΩ, and the buffer Darlington transistor
Set the collector potential of Q ₈ , Q ₉ , Q ₁₀ , and Q ₁₁ to 0V, power supply
When the voltage of V _CC is 30V and the input current I _IN is 200μA, the current transfer ratio (I _OUT /I _IN ) is 0.15%,
This was a significant improvement compared to the current transfer ratio of 4.6% in the second conventional example (shown in FIG. 2).

Note that the present invention applies to the first and second embodiments (third and third embodiments) described above.
It goes without saying that the present invention is not limited to the structure shown in FIG. 4) and can be applied to various modifications without departing from the constituent requirements of the present invention.

As explained above, in the current mirror circuit of the present invention, the level shift transistor is operated by the current flowing through the transistor that supplies the base current of the current mirror transistor, and the emitter potential of the level shift transistor is used to operate the buffer transistor. By creating a reference voltage, there is an effect that it is not influenced by the current amplification factor and the Early effect, thereby reducing errors and reducing voltage loss. Furthermore, since the circuit configuration is simple and power consumption is low, it is easy to integrate the circuit.

[Brief explanation of the drawing]

FIGS. 1 and 2 are circuit diagrams showing first and second examples of conventional current mirror circuits, respectively, and FIGS. 3 and 4 are circuit diagrams showing first and second implementations of the current mirror circuit of the present invention, respectively. FIG. 2 is a circuit diagram of a two-output current mirror circuit showing an example. In the figure, 1, 2, 3, 4... Current mirror circuit, 41, 42... Darlington transistor for buffer, D ₁ ... Diode for level shift, I _IN
…Input current, I _OUT1 , I _OUT2 …Output current, Q ₁ , Q ₂ ,
Q ₃ ... Current mirror transistor, Q ₄ ... Current amplification factor correction transistor, Q ₅ , Q _{6 ... Current direction reversal transistor, Q 7 ...} Level shift transistor, Q ₈ , Q ₉ , Q ₁₀ , Q ₁₁ ... Buffer transistor, R ₁ , R ₂ , R ₃ ... Current mirror resistor,
V _CC …power supply.

Claims (1)

[Scope of Claims] 1: first and second transistors of a first polarity whose bases are interconnected and whose respective emitters are connected to a power supply through respective resistors;
a third transistor of a first polarity whose base and emitter are connected to the collector and base of the first transistor, respectively; and a third transistor whose base and collector are connected to the collector of the third transistor and whose emitter is connected to a reference potential point. a fourth transistor of a second polarity connected, and a fifth transistor of a second polarity, the base of which is connected to the collector of the third transistor, and the emitter of which is connected to the reference potential point.
a sixth transistor of a second polarity, whose base, collector, and emitter are respectively connected to the base of the first transistor, the power supply, and the collector of the fifth transistor; a seventh transistor of a first polarity connected to the emitter of the transistor and whose emitter is connected to the collector of the second transistor, the collector of the first transistor being an input, and the collector of the seventh transistor being connected to the collector of the second transistor; A current mirror circuit characterized by having an output of 2. In the current mirror circuit according to claim 1, the seventh transistor is a Darlington transistor, and a diode is inserted and connected in the forward direction between the emitter of the sixth transistor and the base of the Darlington transistor. A current mirror circuit characterized by: