JP2985280B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for a semiconductor integrated circuit.

The present invention is particularly applied to a semiconductor integrated circuit including an ECL (emitter coupled logic) output circuit.

〔Overview〕

The present invention relates to a semiconductor integrated circuit including an ECL output circuit, wherein a collector is grounded, first and second resistors are respectively connected between a collector and a base, and between a base and an emitter, and a bipolar transistor which takes out an output from the emitter; The current is cut off at the time of "High" level output, and "Low"
By providing a constant current generating circuit for drawing a constant current from the base of the bipolar transistor at the time of level output, low power consumption, high speed, and a small chip area can be achieved.

[Conventional technology]

A so-called BiCMOS logic circuit in which a MOS transistor and a bipolar transistor are mixed on the same chip is entering an area which has been conventionally supported by an ECL logic circuit due to its high speed. Accordingly, the necessity of mixing ECL input / output circuits as an interface with ECL logic circuits has increased for BiCMOS logic circuits mainly having TTL input / output circuits.

FIG. 3 shows a representative example as a response to this request.

In this conventional example, a normal ECL output circuit including NPN-type bipolar transistors 11 to 13, a load resistor _RL, and a constant current generation circuit 14 is configured together with a reference voltage generation circuit 16 that supplies a reference voltage _VREF . Logic amplitude of internal circuit
This is realized by adding a level conversion circuit 15 for converting the amplitude to the logic amplitude of the ECL logic circuit.

That is, logic amplitude V _L of the internal circuit in BiOMOS logic circuit, V _L = | represented by -V _F | V _EE. However V _EE voltage of negative potential power supply, V _F is the base of the bipolar transistor - a forward voltage of the emitter.

Here, assuming that V _EE = 1-5.2V and V _F = 0.8V, V _L = 4.4
V. On the other hand, the logical amplitude of the ECL logic circuit is represented by _{V L = R L · I CS} , usually about 800 mV, about the level conversion circuit 15 of FIG. 3 the logic amplitude V _L of BiCMOS logic circuit described above The method of compressing and outputting to 800mV is adopted.

[Problems to be solved by the invention]

 The conventional example described above has the following disadvantages.

First, the constant current generation circuit 14 always consumes a large amount of power because a current always flows. For this reason, the advantage of the BiCMOS logic circuit in which low power consumption is one of the advantages is impaired.

Second, the high speed of the ECL output circuit cannot be fully utilized because the level conversion circuit 15 is required.

Third, since the reference voltage generation circuit 16 needs to be provided in the chip, the chip area increases.

The object of the present invention is to eliminate the disadvantages mentioned above,
An object of the present invention is to provide a semiconductor integrated circuit having an ECL output circuit, which has low power consumption, is excellent in high-speed operation, and can reduce a chip area.

[Means for solving the problem]

The present invention relates to a first bipolar transistor in which a first resistor and a second resistor are connected between a base and a collector and between a base and an emitter, a collector is connected to a ground potential, and an emitter is connected to an output terminal. A constant current generating circuit for interrupting the current at the time of "high" level output and drawing a constant current from the base of the first bipolar transistor at the time of "low" level output.

Also, the present invention provides the constant current generating circuit, wherein a collector is connected to a base of the first bipolar transistor, an emitter is connected to a power supply via a third resistor, A base circuit connected between the base of the two bipolar transistors and the power supply to determine the base potential of the second bipolar transistor; a P-channel MOS transistor and an N-channel transistor
A gate circuit, which is formed of a series connection circuit with an OS transistor, is connected between the ground potential and the power supply, and has an output connected to the base of the second bipolar transistor.

In the present invention, it is preferable that the base circuit is a diode.

In the present invention, it is preferable that the base circuit is a resistor.

Further, the present invention can include a temperature compensation circuit including a diode and a resistor connected in series between the base of the first bipolar transistor and the ground potential.

[Action]

Bases of first and second bipolar transistors
The forward voltage between the emitters is V _F1 and V _F2 , the voltage drop of the base circuit is V _F3 , and the first, second and third resistors are R.
_Assuming that ₁ , R ₂ and R ₃ , the “high” level output voltage V _OH and the “low” level output voltage V _OL are given by the following equations, respectively.

That is, the output voltage is V _F1 , V _F2 , V _F3 and the resistance ratio R ₁ /
Since it is determined by R ₃ and R ₁ / R ₂ , the influence of variations in manufacturing conditions is extremely reduced, and the level can be set precisely.

Furthermore, the level conversion circuit and the reference voltage generation circuit required in the conventional example are not required, and the current of the constant current generation circuit becomes zero at the time of high level output, so that the power consumption is low, the speed is excellent, In addition, a semiconductor integrated circuit having a small chip area can be realized.

Although it has excellent temperature characteristics, it can be accurately adjusted to, for example, ECL-10KH by adding a temperature compensation circuit.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this first embodiment, the base-collector and base-
A first resistor R ₁ and a second resistor R ₂ respectively between the emitters
There is connected a collector connected to the ground potential GND, and the emitter is a first bipolar transistor 1 of the connected NPN type connected to the load resistor R _L through the output power V _T to the output terminal OUT, and "high" When level output, cut off the current,
A constant current generating circuit 7 for drawing a constant current from the base of the bipolar transistor 1 at the time of "low" level output is provided.

The constant current generating circuit 7 includes an NPN-type second bipolar transistor 3 having a collector connected to the base of the bipolar transistor 1 and an emitter connected to a negative potential power supply _VEE via a _third resistor R3. A diode 2 connected between the base of the bipolar transistor 3 and the negative potential power supply _VEE as a base circuit for determining the base potential of the bipolar transistor 3, and a resistance R of the P-channel MOS transistor 4 and the N-channel MOS transistor 5; ₆ and a ground potential GND and a negative potential power supply V
_And a gate circuit connected between _EE and having an output connected to the base of the bipolar transistor 3.

 Next, the operation of the first embodiment will be described.

First, a case where a signal of a “low” level (〜V _EE ) is input to the input terminal A will be described. When a “low” level signal is input to the input terminal A, the P-channel MOS transistor 4 is turned “ON” and the N-channel MOS transistor 5 is turned “OFF”, whereby the current flows through the diode 2 and the bipolar transistor 3. Are supplied and turned on. At this time, the emitter current I ₃ of the bipolar transistor ₃ becomes It can be expressed as. Here, _VF2 and _VF3 indicate the forward voltage between the base and the emitter of the diode 2 and the bipolar transistor 3, respectively.

The collector current I ₃ ′ is Becomes here, (However, _VF1 is the base of the bipolar transistor 1.
The forward voltage between the emitters, h _FE is the common emitter current amplification factor of each bipolar transistor.) Thinking, Therefore, the “low” level output voltage V _OL is Becomes

Next, when a “high” level signal is input to the input terminal A, the P-channel MOS transistor 4 is turned “OFF” and the N-channel MOS transistor 5 is turned “ON”. 3 is "off". That, I ₃ '= 0, and the base potential V _B of the bipolar transistor 1 is increased. Here, it can be expressed as V ₁ = V _B1 + I _2. Considering that I _B1 ≪I ₁ and calculating the high-level output voltage V _OH , Becomes

As can be seen from the equations (1) and (2), the output levels correspond to the base-emitter forward voltages V _F1 , V _F2 and V
_{Since it is determined by F3} and the resistance ratios R ₁ / R ₃ and R ₁ / R ₂ , the influence of variations in manufacturing conditions is extremely small.

Next, these temperature characteristics will be considered. (1) is differentiated by temperature T a formula, the V _G as a band gap voltage, Therefore, To do The ratio of R ₁ / R ₂ may be set so that At this time, R
_{In addition} to determining the ratio of ₁ / R ₂ , the emitter area of the bipolar transistor 1 is determined so as to be within the specification of V _{OH.
Find F1} .

Furthermore, differentiating equation (2) with temperature T gives: That is, R ₁ / R ₂ determined by the equations (2) and (3)
And the ratio determine the temperature dependence of equation (4).
It has characteristics equivalent to L-10KH.

Also, in equation (1), to meet the _VOL standard,
The resistance ratio R ₁ / R ₃ and bipolar transistors 1 and 3
Is determined, and V _F2 and V _F3 may be obtained.

 FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

Second Embodiment This is used in the first embodiment of FIG. 1, as a base circuit, the resistor R ₅ in place of the diode 2,
Further, the base of the bipolar transistor 1 and the ground potential
And a temperature compensation circuit comprising a series-connected diode 6 and the resistor R ₄ Metropolitan to GND.

In the second embodiment, in order to finely adjust the temperature dependency of V _OH , the current flowing through the resistor R ₁ is reduced at a high temperature by the diode 6 and the resistor R ₄ . As a result, it is possible to accurately meet the ECL-10KH standard.

〔The invention's effect〕

As described above, the present invention has the following effects.

(1) Since a reference voltage generation circuit is unnecessary, a reduction in chip area and power consumption can be achieved.

(2) The constant current generating circuit can be controlled, that is, the current can be cut at the time of _VOL output, and power consumption can be reduced.

(3) Since a level conversion circuit is unnecessary, high-speed operation is possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a second embodiment of the present invention. FIG. 3 is a circuit diagram showing a conventional example. 1, 3, 11 to 13 bipolar transistors, 2, 6 ...
... Diode, 4 ... P-channel MOS transistor, 5
...... N-channel MOS transistor, 7,14 ...... constant current generating circuit, 15 ...... level conversion circuit, 16 ...... reference voltage generating circuit, R ₁ to R ₆ ...... resistance, R _L ...... load resistance, A ... … Input end,
GND: Ground potential, OUT: Output terminal, V _B: Base potential, V _EE: Negative potential power supply, V _T: Output power supply.

Claims (5)

(57) [Claims] A first bipolar transistor having first and second resistors connected between a base and a collector and between a base and an emitter, a collector connected to a ground potential, and an emitter connected to an output terminal, respectively. And a constant current generating circuit that cuts off current at the time of “high” level output and draws a constant current from the base of the first bipolar transistor at the time of “low” level output. A second bipolar transistor having a collector connected to a base of the first bipolar transistor and an emitter connected to a power supply via a third resistor; A base circuit connected between the base of the bipolar transistor and the power supply and determining a base potential of the second bipolar transistor; and a series connection circuit of a P-channel MOS transistor and an N-channel MOS transistor. 2. The semiconductor integrated circuit according to claim 1, further comprising: a gate circuit connected between the power supplies and having an output connected to a base of the second bipolar transistor. 3. The semiconductor integrated circuit according to claim 2, wherein said base circuit is a diode. 4. The semiconductor integrated circuit according to claim 2, wherein said base circuit is a resistor. 5. The temperature compensation circuit according to claim 1, further comprising a temperature compensation circuit including a diode and a resistor connected in series between a base of said first bipolar transistor and said ground potential. Semiconductor integrated circuit.