JP2699821B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit,
In particular, the present invention relates to a level conversion circuit for converting a logic amplitude inside an LSI to a TTL level.

[0002]

2. Description of the Related Art Conventionally, a level conversion circuit for converting a logic amplitude inside an LSI into a transistor / transistor logic level (hereinafter, referred to as a TTL level), as shown in FIG.
In order not to lower the switching operation speed of the transistors, Schottky diodes 20 to 23 having a forward potential of 0.2 to 0.4 V are connected between the bases and collectors of the transistors 6 , 7, 9, and 10, and the transistors are connected. The circuit is not saturated. In the figure, 1 to 10 are transistors, 26 to 33 are resistors, 18 and 19 are diode-connected transistors, 20 to 23 are Schottky barrier diodes, and 40 is a constant current circuit.

Next, the circuit operation will be described. The logic amplitude inside the LSI is input to the input terminal Q and the inverted Q. When the input terminal Q is at a high level, a low level is input to the input terminal Q. Since the transistors 1 and 2 constitute a differential amplifier, the output of the transistor 1 is low and the output of the transistor 2 is high under this input condition. Next, the output of the differential amplifier is output from the collector of the transistor 5 through the level shift circuit including the transistors 3 and 4.

Here, the diode 19 and the transistor 5 change the current flowing through the current mirror circuit 5 and set the resistors 28 and 29 so as to output an amplitude about twice the input terminal signal level. That is, the output high level of the transistor 5 is set to a level higher than the sum of the base-emitter voltages necessary for operating the transistors 6 and 10, and the output low level is set to the transistors 6 and 10
Is set to the level that cuts off. Under this input condition, the output of the transistor 5 becomes low level, and the transistors 6 and 10 are cut off, so that the base potential of the transistor 7 becomes high potential via the resistor 30, so that the transistors 7 and 8 operate. Output terminal is V
_The potential is 2 V _BE below _cc , that is, a high level. next,
In the case opposite to the input condition, the output of the transistor 1 becomes high level, the output of the transistor 2 becomes low level, the output of the transistor 5 becomes high level, and the transistor 6 and the transistor 10 operate.
Since the base potential of the transistors 7 and 8 becomes low, the transistors 7 and 8
Is cut off, and the output terminal goes low.

[0005]

As described above, in this conventional level conversion circuit, the shot level of the forward potential is small to prevent the operation area from entering the saturation area when the base input potential of the transistor becomes high. Key diode 20
To 23 are connected between the base and collector of the transistor to bypass a part of the base current to obtain a high-speed operation.
For this reason, a step of forming a Schottky barrier diode is required, and there are disadvantages in that the number of LSI manufacturing steps increases and the number of level conversion circuit elements also increases.

[0006] As a level conversion circuit in which this disadvantage is improved, there is a level conversion circuit disclosed in Japanese Patent Application Laid-Open No. 61-148919. FIG. 4 is a circuit diagram showing this circuit configuration.
Is characterized in that a diode-connected transistor 14 is provided between the base and collector.

In this circuit, the diode connection of the transistor requires a forward potential of about 0.7 V, and the forward potential between the base and the collector of the transistor 13 is also applied up to the maximum of 0.7 V. And the switching speed becomes slower than when a Schottky diode is used.

[0008] The object of the present invention is to solve these problems,
It is an object of the present invention to provide a level conversion circuit having a simple circuit configuration and high-speed operation.

[0009]

According to the present invention, a first differential amplifier for amplifying an input signal in a level conversion circuit for outputting a transistor / transistor logic level, and an output of the first differential amplifier are provided. And a second input for receiving the output of the emitter follower.
, A control transistor for inputting the output of the second differential amplifier, and a current mirror circuit having an output connected to the input and an output connected to the emitter follower via a resistor. A reference voltage is applied to the other input of the second differential amplifier, and an output of the current mirror circuit is output.

[0010]

According to the structure of the present invention, the current mirror circuit is turned on / off by a control transistor in a resistor provided between the output of the emitter follower for inputting the output of the differential amplifier and the output of the current mirror circuit. As a result, a voltage drop is generated to output the TTL level to the output of the current mirror circuit.

[0011]

FIG. 1 is a circuit diagram of a level conversion circuit according to an embodiment of the present invention. In the figure, 1, 2, 5, 8, 10, 1
1, 12 are transistors, 27 , 30, 31 , 34, 3
5 is a resistor, 19 and 24 are diode-connected transistors, and 40 and 41 are constant current circuits. Transistor 1,
2, a resistor 27 and a constant current circuit 40 constitute a differential amplifier, and transistors 11, 12, and 19 and a constant current circuit 41
Constitutes a second differential amplifier, and transistors 19 and 5
As a result, the first current mirror circuit, the transistors 24 ,
Output unit configured Ri by the 10 and the resistor 30,31,35 of the second current mirror circuit and the transistor 8 by the emitter follower circuit and a resistor 34. Transistor 5 turns on the second-Calais <br/> Ntomira circuit as inputs the output of the second differential amplifier, and a control transistor for turning off
That Do not.

The operation of this circuit will be described. As in the prior art, the logic amplitude inside the LSI is input to the input terminal Q and the inverted Q. When the input terminal Q is at a high level, the output of the transistor 2, which is the output of the differential amplifier, is at a high level, and the emitter voltage of the transistor 8 is further reduced by the forward potential between the base and the emitter. The emitter of the transistor 8 is connected to one input of a second differential amplifier. The other input of the second differential amplifier is connected to a reference voltage V.
_REF is connected, and the reference voltage V _REF is set to the midpoint potential of the amplitude of the emitter output of the transistor 8.

Therefore, under this input condition, the transistor 12 is cut off and the transistor 11 operates, so that the transistors 19 and 5 operate. Transistor 1
Since transistors 9 and 5 constitute a current mirror circuit, the same current as that of the constant current circuit 41 is applied to the transistor 5 by the resistor 30.
_Supplied from V _cc through The resistor 30 is a transistor 5
Are cut off, the transistors 24, 10
And a current mirror circuit consisting of resistor 31 and 35 is operated, so when the transistor 5 is operated is set to the condition in which the current mirror circuit is stopped, the input terminal Q
When the level is high, the current mirror circuit stops, the output terminal goes high, and an output voltage V _OH given by the following equation is obtained.

V _OH = V _cc −V _BE −R ₃₄ × I _O (1) where I _O is an output current, V _BE is a forward potential between the base and the emitter of the transistor 8, and R ₃₄ is a resistor. 34, and when V _cc = 5 V and output current = 0, the output potential becomes the maximum value and V _OHmax = 4.3 V according to the equation (1).

Next, when the input terminal Q is at a low level, the output of the transistor 2 is at a low level, and the emitter of the transistor 8 is also at a low level. As a result, in the second differential amplifier, the transistor 12 operates and the transistor 11 is cut off, so that the transistors 19 and 5 are also cut off, and the current mirror including the transistors 24 and 10 and the resistors 31 and 35 operates and the resistor output current flows through the 34, the output V _OL output terminals is given by the following equation becomes a low level. Where _VL is the output amplitude voltage of the differential amplifier, and V _BE is
The forward potential between the base and the emitter of the transistor 8 is used.

V _OL = V _cc −V _BE −V _L −R ₃₄ × (I ₀ + I ₁ ) (2) In this circuit, the condition that the transistor 5 is not saturated when the output terminal is at a high level, and the output The resistor 3 satisfies the condition that the transistor 10 does not saturate when the terminal is at a low level.
0, 32, 34, 35 and currents I ₁ , I ₂ , I ₃ are set. That is, when the output terminal is at a high level, if the current ratio of the transistors 19 and 5 is 1: 1, the constant current circuit 41
The current I ₃ may be a value shown by the following equation. Here, the base potential of the transistor 10 is V ₁ .

I ₃ = ( _Vcc− V ₁ ) / R _{30 (} 0.7 V> V ₁ > 0.3 V) (3) Next, when the output terminal is at a low level, V _BE ′ Is the base-emitter voltage of transistor 24, resistors 34, 3
0 may be set to a value represented by the following equation. Where I0 = 0
You.

R ₃₄ = (V _cc −V _L −V _BE −V _OL ) / I ₁ (V _OL = 0.4) (4) R ₃₀ = ｛V _cc − (V _BE ′ + R ₃₁₎ (I ₂ )｝ / I ₂ (5) In the following, using specific numerical values, when the output terminal is at a low level, V _cc = 5 V and V _L = 0.4 V , V _BE =
When V _BE '= 0.7 V and V _OL = 0.4 V, the transistor 2
The current value I ₂ of the current mirror circuit according to 4, 10 and
Let I ₁ be I ₂ : I ₁ = 1: 2, R ₃₁ = 132Ω, R ₃₅
= 65Ω and I ₁ = 4 mA, R ₃₄ = 875 Ω and R ₃₀ = 2.02 KΩ from the equations (4) and (5).

[0019] V of the base potential of this time, the transistor 10
₁ = V _BE '+ R ₃₁ × I ₂ = 0.96 V and collector potential
V _OL = 0.4V of. Therefore, the base of transistor 10
The collector forward bias V _B10 is V _B10 = V ₁ −V _OL =
0.56 V, and the transistor 10 does not saturate. If the resistance 35 is 32.5Ω, it can be further reduced to V _B10 = 0.43V.

Next, when the output terminal is at a high level, _{Vcc =}
Assuming that the current ratio of the current mirror circuit formed by the transistors 19 and 5 is 1: 1 at 5 V and V ₁ = 0.3 V, from the equation (3), I ₃ = 4.7 V / 2.02 KΩ = 2.3 mA. If the constant current circuit 41 is set, V ₁ = 0.3 V, and the current mirror circuit formed by the transistors 24 and 10 is cut off. At this time, the base of transistor 5
The collector forward bias V _B5 is diode-connected
Assuming that the forward voltage of the transistor 19 is V _B , V _B5 = V
_B− 0.3V = 0.4V, and the transistor 5 does not saturate.

The current I ₃ can be reduced by inserting a resistor into the emitters of the transistors 19 and 5 to obtain a current ratio. In this case, increased emitter potential rise only V _B5 of the transistor 5 is, but the transistor 5 be elevated V ₁ within the range of (3) the conditions _{(0.7 V> V 1> 0} . 5V) It does not saturate.

FIG. 2 is a circuit diagram of a level conversion circuit according to a second embodiment of the present invention. This embodiment differs from the first embodiment in that a resistor 26 is provided at the output of the transistor 1 constituting the differential amplifier, and that the transistor 4 and the constant current circuit 42
Is provided, the input is connected to the output of the transistor 1, and the output is connected to the input of the transistor 11 constituting the second differential amplifier.
Others are the same as the first embodiment.

In this embodiment, since the inverted output of the differential amplifier is input to the input of the transistor 11 of the second differential amplifier via the transistor 4, the reference voltage V _REF is applied as in the first embodiment. There is a feature that there is no need to provide.
Further, since the differential input voltage of the second differential amplifier is doubled as compared with the first embodiment, there is a feature that the speed of the second differential amplifier is increased.

[0024]

As described above, according to the present invention, a potential effect is produced by turning on and off a current mirror circuit on a resistor provided between an output of an emitter follower and an output of a current mirror circuit, thereby producing a current mirror circuit. Since the output signal is output to the output of the above, a level conversion circuit having a TTL output level can be configured without using a Schottky diode. Also, since the output high level is 0.7 V higher than the conventional one, the TTL level is maintained even when the power supply voltage is reduced.
There is an unprecedented feature that a level is output, and there is an unprecedented feature that an output high level and an output low level can be changed by changing circuit constants.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a level conversion circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a level conversion circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of an example of a conventional level conversion circuit.

FIG. 4 is a partial circuit diagram of an improved conventional level conversion circuit.

[Explanation of symbols]

 1-14 Transistor 18, 19, 24 Diode-connected transistor 20-23 Schottky diode 26-36 Resistance 40-42 Constant current circuit

Claims (2)

(57) [Claims] In a level conversion circuit for outputting a transistor / transistor logic level, a first differential amplifier for amplifying an input signal, an emitter follower for inputting an output of the first differential amplifier, and an emitter follower for inputting an output of the first differential amplifier A second differential amplifier for receiving the output of the second differential amplifier, a control transistor for receiving the output of the second differential amplifier, an output of the control transistor connected to the input, and an output connected to the emitter follower via a resistor. A level conversion circuit comprising: a reference voltage applied to the other input of the second differential amplifier; and an output of the current mirror circuit as an output. 2. A second emitter follower having the other output of the first differential amplifier as an input, the output of the second emitter follower being connected to the other input of the second differential amplifier. The level conversion circuit according to claim 1.