JPS6360554A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To reduce the area of a memory cell by electrically connecting a substrate region in an FET to a semiconductor substrate and positioning one part of one conduction electrode for the FET connected to a bit line onto a trench CONSTITUTION:A conductor layer 13 is arranged on the inner side wall of a trench through an insulating film 19 and constitute a charge storage region. and makes a round along the outer circumference of a cell, and a conductor layer 14 is disposed to the charge storage region through the insulating film 19 and organize a cell plate, and supplied with fixed potential. A P-type region 22 constructs a substrate region in an FET, and is connected electrically to a P-type substrate 11 through a P-type region 12. An N-type region 23 constitutes a first conduction electrode for the FET, and a bit line organized of a conductor layer 27 is connected to the N-type region 23. Accordingly, cells do not interfere mutually, large cell capacitance is acquired by shallow trench depth, a soft error rate is reduced, an element isolation region is made unnecessary, and the area of the cell can be minimized.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor memory cell suitable for high integration.

(Prior art and its problems) A charge storage region is placed on the inner wall of a groove formed on the surface of a semiconductor substrate along the outer periphery with an insulating film interposed therebetween, and a charge storage region is placed in the same trench with an insulating film interposed therebetween. MO5FEr placed on the semiconductor substrate surface surrounded by grooves
A one-transistor, one-capacitor type memory cell consisting of
EDM) Abstract P, 240-243, it has been proposed as 'IVEC cell' by Nakajima et al. FIG. 2(a) is a sectional view of the IVEC cell in the bit line direction, and FIG. 2(b) is a sectional view taken along line AA' in FIG. 2(a) in the word line direction.

The charge storage region of the IVEC cell is formed by a conductor J placed on the inner wall of a groove formed on the surface of the semiconductor substrate 11 with an insulating film 19 interposed therebetween.
i13, and goes around the outer periphery of the cell. The cell plate has an insulating film 19 for the charge storage region.
It consists of a conductor cable 14 placed through the capacitor, and is supplied with a constant voltage. A MOSFET for switching is formed by an N-type region 23 forming a first current-carrying electrode, an N-type region 20 forming a second current-carrying electrode, and a conductor layer 25 forming a word line.
The second conductive electrode is connected to the conductor layer 27 constituting the bit line, and the second conductive electrode is connected to the insulating film 1 on the inner wall of the groove.
9 is removed and connected to the charge storage region.

The main features of the IVEC cell are that no inter-cell interference occurs, a large cell capacity can be obtained with a shallow trench depth, a low soft error rate, and no element isolation region is required.

However, since the IVEC cell has a groove formed on the surface of the semiconductor substrate along the outer periphery, one bit line contact must be formed per cell, which is a major obstacle to miniaturizing the cell area. There is. Furthermore, when the conductor layer 13 constituting the charge storage region has a high potential, the semiconductor interface on the side surface of the groove tends to be in an inverted state. Then the MO for switching
A leakage current flows through the 5FET, deteriorating the information retention characteristics.

Therefore, the purpose of the present invention is to eliminate these conventional drawbacks, thereby eliminating interference between cells, obtaining large cell capacity with a shallow trench depth, having a low soft error rate, and eliminating the need for element isolation regions. Moreover, it is an object of the present invention to provide a semiconductor memory cell that requires only one bit line contact per two cells and has good information retention characteristics.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the semiconductor memory cell provided by the present invention has a semiconductor memory cell that is arranged on the inner wall of a groove formed on the surface of a semiconductor substrate along the outer periphery with an insulating film interposed therebetween. It consists of a charge storage region, a cell plate disposed in the trench with an insulating film interposed in relation to the charge storage region, and an FET formed on a semiconductor layer grown on a semiconductor substrate or an insulating film.
a substrate region of Er is electrically connected to the semiconductor substrate;
At least a portion of one current-carrying electrode of the FET connected to the bit line is located above the groove.

(Example) Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1(a) is a sectional view in the bit line direction of an embodiment of the present invention, and FIG. 1(b) is a sectional view in the word line direction taken along line AA' in FIG. 1(a). Note that FIG. 1 shows an embodiment corresponding to a folded-rad bit line configuration.

11 is a P-type substrate, and 12 is a P-type head area. Conductor 1
13 is arranged on the inner wall of the groove with an insulating film 19 interposed therebetween;
It constitutes a charge storage region and runs around the outer periphery of the cell. The conductor layer 14 is arranged with an insulating film 19 interposed between the charge storage region, constitutes a cell plate, and is supplied with a constant potential. Furthermore, by increasing the impurity concentration of the P-type substrate 11, the P-type substrate can also have the role of a cell plate. Conductor layers L5, 16, 17, 1
8 constitutes a charge storage region of an adjacent cell. N-type region 2
0 constitutes a connecting portion that electrically connects the second current-carrying electrode of the FET and the charge storage region. The P-type region 21 is a region for cutting off the leakage current bus of the switching FBI in the event that the semiconductor interface on the side surface of the groove is inverted, and has a higher impurity concentration than the P-type head region 12.

The P-type head area 22 constitutes the substrate area of the FET, and the P-type head area 1
It is electrically connected to the P-type substrate 11 via 2. N
The mold region 23 constitutes the second current-carrying electrode of the FET. The N-type region 24 constitutes the second current-carrying electrode of the FET, and the N-type region 20
It is connected to the charge storage region through. Here, the P-type head region 22, the N-type region 23, and the N-type region 24 are formed on a semiconductor substrate or a semiconductor layer grown on an insulating film. The conductor layer 25 constitutes the gate electrode of the FET and also serves as word line wiring. The conductor layer 26 is a word line wiring for accessing adjacent cells. The conductor layer 27 constitutes a bit line, and F
ET's 1st letter M, read by 1 pole. 28 and 29 are insulating films.

The method of operation of the semiconductor memory cell of the present invention is similar to that of an IVEC cell, and the same as that of a normal one-transistor, one-capacitor type memory cell.

For convenience of explanation, an example in which an N-type channel MO5FET is used as the FET has been described above, but the present invention is applicable to other FEs.
It can also be applied when T is used. Furthermore, FETs can be formed not only in epitaxially grown semiconductor layers, but also in various semiconductor layers, such as polycrystalline semiconductor layers, those processed by appropriate methods, and those made into single crystals by further appropriate methods. Can be done.

(Effects of the Invention) The semiconductor memory cell of the present invention does not cause inter-cell interference, has a large cell capacity with a shallow groove depth, has a small soft error rate, and does not require an element isolation region. Moreover, since the bit line contact can be formed on the groove, the bit line contact can be shared with adjacent cells, and the cell area can be miniaturized. Further, even if the semiconductor interface on the side surface of the groove should be inverted, the leakage path of the switching FEr can be cut, so that the information retention characteristics will not deteriorate. Furthermore, since a constant voltage is supplied to the substrate region of the switching FET, malfunctions will not occur. As described above, the effects of the present invention are very large.

[Brief explanation of drawings]

FIG. 1(a) is a sectional view in the bit line direction of an embodiment of the present invention, FIG. 1(b) is a sectional view in the word line direction taken along line AA' in FIG. Figure 2 (a) is an IVE
A sectional view of the C cell in the bit line direction, FIG. 2(b) is a sectional view in the word line direction taken along line AA' in FIG.

Claims (1)

[Claims] a charge storage region disposed on an inner wall of a groove formed on a surface of a semiconductor substrate along an outer periphery with an insulating film interposed therebetween; a cell plate disposed in the groove with an insulating film interposed between the charge accumulation region and the semiconductor substrate; a FET formed on a semiconductor layer grown on or on an insulating film, the substrate region of this FET is electrically connected to the semiconductor substrate, and at least one current-carrying electrode of one of the FETs is connected to a bit line. A semiconductor memory cell, a portion of which is located above the trench.