JPS6360554A - Semiconductor memory cell - Google Patents
Semiconductor memory cellInfo
- Publication number
- JPS6360554A JPS6360554A JP61204898A JP20489886A JPS6360554A JP S6360554 A JPS6360554 A JP S6360554A JP 61204898 A JP61204898 A JP 61204898A JP 20489886 A JP20489886 A JP 20489886A JP S6360554 A JPS6360554 A JP S6360554A
- Authority
- JP
- Japan
- Prior art keywords
- region
- cell
- fet
- insulating film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000009825 accumulation Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 abstract description 14
- 238000002955 isolation Methods 0.000 abstract description 4
- 210000004027 cell Anatomy 0.000 description 31
- 239000003990 capacitor Substances 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 210000003771 C cell Anatomy 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
- H10B12/373—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate the capacitor extending under or around the transistor
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は高集積化に適した半導体メモリセルに関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor memory cell suitable for high integration.
(従来技術とその問題点)
外周に沿って半導体基板表面に形成した溝内側壁に絶縁
膜を介して配置した電荷蓄積領域と、同じ溝内に電荷蓄
積領域に対して絶縁膜を介して配置したセルプレートと
、溝に囲まれた半導体基板表面に配置したMO5FEr
で構成される1トランジスター1キヤパシタ型メモリセ
ルが1984年に開催された国際電子素子会91 (I
EDM )のアブストラクトP、 240〜243に中
島蕃等によって’ IVECセル」として提案されてい
る。第2図(a)はIVECセルのビット線方向の断面
図、同図(b)は同図(a)のA−A’において切り出
したワード線方向の断面図である。(Prior art and its problems) A charge storage region is placed on the inner wall of a groove formed on the surface of a semiconductor substrate along the outer periphery with an insulating film interposed therebetween, and a charge storage region is placed in the same trench with an insulating film interposed therebetween. MO5FEr placed on the semiconductor substrate surface surrounded by grooves
A one-transistor, one-capacitor type memory cell consisting of
EDM) Abstract P, 240-243, it has been proposed as 'IVEC cell' by Nakajima et al. FIG. 2(a) is a sectional view of the IVEC cell in the bit line direction, and FIG. 2(b) is a sectional view taken along line AA' in FIG. 2(a) in the word line direction.
IVECセルの電荷蓄積領域は半導体基板11の表面に
形成した溝内側壁に絶縁膜19を介して配置した導体J
i13で構成されており、セルの外周に沿って一周して
いる。セルプレートは電荷蓄積領域に対して絶縁膜19
を介して配置した導体届14で構成されており、一定電
圧が供給されている。第1通電電極を構成するN型領域
23と第2通電電極を構成するN型領域20とワード線
を構成する導体層25でスイッチング用のMOSFET
が構成され、第2通電電極はビット線を構成する導体層
27に接続され、第2通’を電極は溝内側壁の絶縁膜1
9の一部を除去して電荷蓄積領域に接続されている。The charge storage region of the IVEC cell is formed by a conductor J placed on the inner wall of a groove formed on the surface of the semiconductor substrate 11 with an insulating film 19 interposed therebetween.
i13, and goes around the outer periphery of the cell. The cell plate has an insulating film 19 for the charge storage region.
It consists of a conductor cable 14 placed through the capacitor, and is supplied with a constant voltage. A MOSFET for switching is formed by an N-type region 23 forming a first current-carrying electrode, an N-type region 20 forming a second current-carrying electrode, and a conductor layer 25 forming a word line.
The second conductive electrode is connected to the conductor layer 27 constituting the bit line, and the second conductive electrode is connected to the insulating film 1 on the inner wall of the groove.
9 is removed and connected to the charge storage region.
IVECセルの主な特徴は、セル間干渉が生じず、浅い
溝深きで大きなセル容量が得られ、ソフトエラー率が小
さく、素子分離領域が不要であることにある。The main features of the IVEC cell are that no inter-cell interference occurs, a large cell capacity can be obtained with a shallow trench depth, a low soft error rate, and no element isolation region is required.
ところが、IVECセルは外周に沿って半導体基板表面
に溝を形成しているために、セル当り1つのビット線コ
ンタクトを形成しなければならず、セル面積の微小化に
対して大きな障害になっている。また電荷蓄積領域を構
成する導体層13が高電位の場合に、溝側面の半導体界
面が反転状態になりやすい。するとスイッチング用MO
5FETにリーク電流が流れて情報保持特性が悪化して
しまう。However, since the IVEC cell has a groove formed on the surface of the semiconductor substrate along the outer periphery, one bit line contact must be formed per cell, which is a major obstacle to miniaturizing the cell area. There is. Furthermore, when the conductor layer 13 constituting the charge storage region has a high potential, the semiconductor interface on the side surface of the groove tends to be in an inverted state. Then the MO for switching
A leakage current flows through the 5FET, deteriorating the information retention characteristics.
そこで本発明の目的は、このような従来の欠点を除去せ
しめて、セル間干渉が生じず、浅い溝深さで大きなセル
容量が得られ、ソフトエラー率が小さく、素子分離領域
が不要であり、しかも2つのセル当たり1つのビット線
コンタクトしか必要とせず、情報保持特性が良好な半導
体メモリセルを提供することにある。Therefore, the purpose of the present invention is to eliminate these conventional drawbacks, thereby eliminating interference between cells, obtaining large cell capacity with a shallow trench depth, having a low soft error rate, and eliminating the need for element isolation regions. Moreover, it is an object of the present invention to provide a semiconductor memory cell that requires only one bit line contact per two cells and has good information retention characteristics.
(問題点を解決するための手段)
前述の問題点を解決するために本発明が提供する半導体
メモリセルは、外周に沿って半導体基板表面に形成した
溝内側壁に絶縁膜を介して配置した電荷蓄積領域と、前
記溝内に前記電荷蓄積領域に対して絶縁膜を介して配置
したセルプレートと、半導体基板上または絶縁膜上に成
長させた半導体層に形成したFETとからなり、このF
Erの基板領域が前記半導体基板に電気的に接続され、
ビット線に接続される前記FETの一方の通電電極の少
なくとも一部が前記溝の上に位置することを特徴とする
。(Means for Solving the Problems) In order to solve the above-mentioned problems, the semiconductor memory cell provided by the present invention has a semiconductor memory cell that is arranged on the inner wall of a groove formed on the surface of a semiconductor substrate along the outer periphery with an insulating film interposed therebetween. It consists of a charge storage region, a cell plate disposed in the trench with an insulating film interposed in relation to the charge storage region, and an FET formed on a semiconductor layer grown on a semiconductor substrate or an insulating film.
a substrate region of Er is electrically connected to the semiconductor substrate;
At least a portion of one current-carrying electrode of the FET connected to the bit line is located above the groove.
(実施例)
以下本発明の実施例について図面を参照して詳細に説明
する。(Example) Examples of the present invention will be described in detail below with reference to the drawings.
第1図(a)は本発明の一実施例のビット線方向の断面
図、同図(b)は同図(a)のA−A’において切り出
したワード線方向の断面図である。なお第1図にはフォ
ールディラド・ビット線構成に対応した実施例を示して
いる。FIG. 1(a) is a sectional view in the bit line direction of an embodiment of the present invention, and FIG. 1(b) is a sectional view in the word line direction taken along line AA' in FIG. 1(a). Note that FIG. 1 shows an embodiment corresponding to a folded-rad bit line configuration.
11はP型基板であり、12はP型頭域である。導体1
13は溝内側壁に絶縁膜19を介して配置されており、
電荷蓄積領域を構成し、セルの外周に沿って一周してい
る。導体層14は電荷蓄積領域に対して絶縁膜19を介
して配置されており、セルプレートを構成し、一定電位
が供給されている。またP型基板11の不純物濃度を高
くすることで、P型基板にもセルプレートの役割を持た
せることができる。導体層L5 、16 、17 、1
8は隣りのセルの電荷蓄積領域を構成する。N型領域2
0はFETの第2通電電極と電荷蓄積領域を電気的に接
続させる接続部を構成する。P型領域21は、溝側面の
半導体界面が万一反転状態になった場合にスイッチング
用FBIのリーク電流のバスをカットさせるための領域
であり、P型頭域12よりも不純物濃度が高い。11 is a P-type substrate, and 12 is a P-type head area. Conductor 1
13 is arranged on the inner wall of the groove with an insulating film 19 interposed therebetween;
It constitutes a charge storage region and runs around the outer periphery of the cell. The conductor layer 14 is arranged with an insulating film 19 interposed between the charge storage region, constitutes a cell plate, and is supplied with a constant potential. Furthermore, by increasing the impurity concentration of the P-type substrate 11, the P-type substrate can also have the role of a cell plate. Conductor layers L5, 16, 17, 1
8 constitutes a charge storage region of an adjacent cell. N-type region 2
0 constitutes a connecting portion that electrically connects the second current-carrying electrode of the FET and the charge storage region. The P-type region 21 is a region for cutting off the leakage current bus of the switching FBI in the event that the semiconductor interface on the side surface of the groove is inverted, and has a higher impurity concentration than the P-type head region 12.
P型頭域22はFETの基板領域を構成し、P型頭域1
2を介してP型基板11に電気的に接続されている。N
型領域23はFETの第2通電電極を構成する。N型領
域24はFETの第2通電電極を構成し、N型領域20
を介して電荷蓄積領域に接続きれている。ここでP型頭
域22、N型領域23、N型領域24は半導体基板ある
いは絶縁膜上に成長させた半導体層に形成する。導体層
25はFETのゲート電極を構成し、ワード線配線も兼
ねる。導体層26は隣りのセルをアクセスするためのワ
ード線配線である。導体層27はビット線を構成し、F
ETの第1通M、1極に接読される。28 、29は絶
縁膜である。The P-type head area 22 constitutes the substrate area of the FET, and the P-type head area 1
It is electrically connected to the P-type substrate 11 via 2. N
The mold region 23 constitutes the second current-carrying electrode of the FET. The N-type region 24 constitutes the second current-carrying electrode of the FET, and the N-type region 20
It is connected to the charge storage region through. Here, the P-type head region 22, the N-type region 23, and the N-type region 24 are formed on a semiconductor substrate or a semiconductor layer grown on an insulating film. The conductor layer 25 constitutes the gate electrode of the FET and also serves as word line wiring. The conductor layer 26 is a word line wiring for accessing adjacent cells. The conductor layer 27 constitutes a bit line, and F
ET's 1st letter M, read by 1 pole. 28 and 29 are insulating films.
本発明の半導体メモリセルの動作方法はIVECセルと
同様であり、通常の1トランジスター1キヤパシタ型メ
モリセルと同様である。The method of operation of the semiconductor memory cell of the present invention is similar to that of an IVEC cell, and the same as that of a normal one-transistor, one-capacitor type memory cell.
以上説明の便宜上FETにN型チャネルMO5FETを
使用した実施例について説明したが、本発明は他のFE
Tを用いた場合にも適用できる。またFETはエピタキ
シャル成長させた半導体層たけでなく、多結晶半導体層
や、それを適当な方法で処理したものや、さらに適当な
方法で単結晶化させたものなど、さまざまな半導体層に
形成することができる。For convenience of explanation, an example in which an N-type channel MO5FET is used as the FET has been described above, but the present invention is applicable to other FEs.
It can also be applied when T is used. Furthermore, FETs can be formed not only in epitaxially grown semiconductor layers, but also in various semiconductor layers, such as polycrystalline semiconductor layers, those processed by appropriate methods, and those made into single crystals by further appropriate methods. Can be done.
(発明の効果)
本発明の半導体メモリセルは、セル間干渉が生じず、浅
い溝深さで大きなセル容量が得られ、ソフトエラー率が
小さく、素子分離領域が不要である。しかもビット線コ
ンタクトを溝の上に形成できるのでビット線コンタクト
を隣りのセルと共通にでき、セル面積の微少化ができる
。また溝側面の半導体界面が万一反転状態になった場合
でもスイッチング用FErのリークパスをカットできる
ため情報保持特性が悪化することはない。さらにスイッ
チング用FETの基板領域は一定電圧が供給されている
ために誤動作することもない。このように本発明の効果
は非常に大きい。(Effects of the Invention) The semiconductor memory cell of the present invention does not cause inter-cell interference, has a large cell capacity with a shallow groove depth, has a small soft error rate, and does not require an element isolation region. Moreover, since the bit line contact can be formed on the groove, the bit line contact can be shared with adjacent cells, and the cell area can be miniaturized. Further, even if the semiconductor interface on the side surface of the groove should be inverted, the leakage path of the switching FEr can be cut, so that the information retention characteristics will not deteriorate. Furthermore, since a constant voltage is supplied to the substrate region of the switching FET, malfunctions will not occur. As described above, the effects of the present invention are very large.
第1図(a)は本発明の一実施例のビット線方向の断面
図、第1図(b)は第1図(a)のA−A’において切
り出したワード線方向の断面図、第2図(a)はIVE
Cセルのビット線方向の断面図、第2図(b)は第2図
(、)のA−A’において切り出したワード線方向の断
面図である。FIG. 1(a) is a sectional view in the bit line direction of an embodiment of the present invention, FIG. 1(b) is a sectional view in the word line direction taken along line AA' in FIG. Figure 2 (a) is an IVE
A sectional view of the C cell in the bit line direction, FIG. 2(b) is a sectional view in the word line direction taken along line AA' in FIG.
Claims (1)
縁膜を介して配置した電荷蓄積領域と、前記溝内に前記
電荷蓄積領域に対して絶縁膜を介して配置したセルプレ
ートと、半導体基板上または絶縁膜上に成長させた半導
体層に形成したFETとからなり、このFETの基板領
域が前記半導体基板に電気的に接続され、ビット線に接
続される前記FETの一方の通電電極の少なくとも一部
が前記溝の上に位置することを特徴とする半導体メモリ
セル。a charge storage region disposed on an inner wall of a groove formed on a surface of a semiconductor substrate along an outer periphery with an insulating film interposed therebetween; a cell plate disposed in the groove with an insulating film interposed between the charge accumulation region and the semiconductor substrate; a FET formed on a semiconductor layer grown on or on an insulating film, the substrate region of this FET is electrically connected to the semiconductor substrate, and at least one current-carrying electrode of one of the FETs is connected to a bit line. A semiconductor memory cell, a portion of which is located above the trench.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61204898A JPH0797624B2 (en) | 1986-08-29 | 1986-08-29 | Semiconductor memory cell |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61204898A JPH0797624B2 (en) | 1986-08-29 | 1986-08-29 | Semiconductor memory cell |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6360554A true JPS6360554A (en) | 1988-03-16 |
JPH0797624B2 JPH0797624B2 (en) | 1995-10-18 |
Family
ID=16498223
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61204898A Expired - Lifetime JPH0797624B2 (en) | 1986-08-29 | 1986-08-29 | Semiconductor memory cell |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0797624B2 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60136366A (en) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS60236261A (en) * | 1984-04-25 | 1985-11-25 | シーメンス、アクチエンゲゼルシヤフト | 1-transistor memory cell and method of producing same |
JPS6188554A (en) * | 1984-10-08 | 1986-05-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory and manufacture thereof |
-
1986
- 1986-08-29 JP JP61204898A patent/JPH0797624B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60136366A (en) * | 1983-12-26 | 1985-07-19 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS60236261A (en) * | 1984-04-25 | 1985-11-25 | シーメンス、アクチエンゲゼルシヤフト | 1-transistor memory cell and method of producing same |
JPS6188554A (en) * | 1984-10-08 | 1986-05-06 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor memory and manufacture thereof |
Also Published As
Publication number | Publication date |
---|---|
JPH0797624B2 (en) | 1995-10-18 |
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