JPS6359022A - A/d converter - Google Patents

Abstract

PURPOSE:To improve the bit accuracy and the reliability against environmental change by using each A/D converter to apply A/D conversion to a signal clamped at upper and lower limits of an input power range of two A/D converters to connect the two A/D converters in cascade without error. CONSTITUTION:A pulse of a signal (b) is clamped to a lower limit Vref1 in a clamp circuit 3 to be a signal (d) and a pulse of the signal (b) is clamped to the upper limit Vref2 in a clamp circuit 4 to be a signal (c). The signals (d), (c) are inputted respectively to A/D converters 6, 7, where the signals are subject to A/D conversion. Thus, a video signal having a higher potential than a summing pulse potential is converted into a digital signal by the A/D converter 6 and a video signal lower than the summing pulse potential is converted into a digital signal by the A/D converter 7, they are added by an arithmetic processing unit 8 and the result goes to an (n+1)-bit digital signal. Thus, the accuracy is doubled in comparison with the single operation.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention is applicable to analog signals, particularly analog video signals 2.
- This relates to an A/D converter that converts a signal into a digital signal.

2. Description of the Related Art An A/D converter that converts an analog video signal into a digital one is required to have both high speed and high precision.

Accuracy is determined by the number of bits of the converted digital signal1
Every additional bit increases the performance by a factor of 2.

However, with current semiconductor technology, high-speed A/
Realizing a D converter is extremely difficult. Therefore, several proposals have been made to improve accuracy by using a high-speed A/D converter with a small number of bits.

As a method to improve the bit precision of conventional A/D converters, see the Technical Report of the Television Society of Japan VOL.

9. Notification 14 Shown in PP57-62.

FIG. 3 shows a block diagram of this conventional A/D converter, in which 1 is an amplifier with a gain of 2, 4 is a clamp circuit that clamps the DC potential of the video signal to the potential of a reference voltage source 9, and 5 is a block diagram of this conventional A/D converter. is a synchronization signal generator that supplies clamp pulses to the clamp circuit 4 and driving 3...- diclock signals to the A/D converters 6 and 7; 6 and 7 are A that convert analog signals to n-bit digital signals; /D converter, 9, 10, 11 is the input voltage range of A/D converter 6, 7 (this is also called reference voltage range)
8 is an A/D converter 6. 12 is a level shift circuit that shifts the clock level input to the A/D converter 6 to an appropriate level; 13 is an A/D converter 6;
This is a level shift circuit that changes the level of the digital signal of the D converter 6.

The operation of the A/D converter configured as above will be described below.

The video signal is amplified twice by the amplifier 1, and then the blanking portion is clamped by the clamp circuit 4 to a potential vref determined by the reference voltage source 9, and is input to the A/D converter. The A/D converter 6 uses the potential vrefs of the reference voltage source 11 and the potential vrefz of the reference voltage source 10.
The potential difference (vrlsf!1-vrof2) determined by is converted into an n-bit digital signal.

Same<The A/D converter 7 has a potential difference (vrefz're
f+) into n bits. Each A/D converter 6, 7
The digital signals converted in are added in the arithmetic processor 8 (
n-4-1) digital signal.

Now, the accuracy of the A/D converter configured as above will be described. First, for comparison, the accuracy when the A/I converter 7 is operated alone will be described. Figure 4 is A/
In the configuration where the D converter 7 is provided alone, as shown in FIG. 5(a), an analog video signal between the potential differences (vr6f2-vrof,) is converted into an n-bit digital signal. On the other hand, in the case of FIG. 3, the video signal amplified twice by the amplifier 1 is input to the A/D converter 6.7. ) in Figure 5, even if the same signal as in Figure 5(A) is input (v
refs-vrefz )-(vrof2-vrefl
), the lower half is sent to the A/D converter, and the upper half is converted to an n-bit digital signal by the A/D converter 6. The signal obtained by adding these is n+
It becomes 1 bit. Therefore, even if the same analog signal is input as in the case where the A/D converter is used alone, it will be converted to an (n+1) bit digital signal, and the accuracy will be doubled.

In this way, the accuracy of the A/D converter can be improved by the configuration shown in FIG. The configuration shown in this conventional example requires two n-pit A/D converters to improve 1-bit accuracy, but it is much more effective than realizing a high-speed n+1-bit A/D converter. be. And you can use the same technique to get as much precision as you need.

Problems to be Solved by the Invention However, the configuration shown above has the following problems.

Generally, an A/D converter can achieve accuracy only when the input voltage range is set to a predetermined value, but it cannot be set arbitrarily. By the way, in the conventional configuration shown in FIG. 3, the A/D converter 6 compares the upper and lower limits of the input voltage range with the input voltage range of the A/D converter 7, and
It has to be made higher. However, as mentioned above, there is an appropriate setting value for the input voltage range, so in the end, for example, by increasing the power supply voltage and ground of the A/D converter 7 by vrof2, the input voltage for the A/D converter 7 becomes It is necessary to ensure that the range is as high as vrc, f2 as the set value.

Items that require high accuracy, such as A/D converters, are most stable when operated with the ground as a reference, and the conventional configuration not only increases the number of power supplies but also degrades stability and accuracy. Furthermore, when the power supply voltage changes, the level of the clock input to the A/D converter 6 and the level of the digital signal output must be shifted.
．． 13 is required. Level-shifting high-speed digital signals requires a temporary circuit scale.

In this way, the accuracy of the conventional A/D converter can be theoretically improved by twice, but this results in an increase in stability and peripheral circuit scale, and the ability cannot be fully demonstrated.

In view of these points, the present invention has high stability, can easily implement peripheral circuits, and fully exhibits theoretical performance7.

An object of the present invention is to provide an A/D converter that performs the following functions.

Means for Solving the Problems In order to achieve the above object, the present invention includes an adder that applies a pulse during the blanking period of a video signal, a first and second DC power supply, and a pulse portion of the output of the adder. first and second clamp circuits that are clamped by the first and second DC power supplies, respectively; the output of the first clamp circuit is used as an input signal; and the first DC power supply is used as the lower limit of the input voltage range. a first A/D converter, a second A/D converter that uses the output of the second clamp circuit as an input signal and uses the second DC power supply as the upper limit of the input voltage range; ．． Second
The configuration includes an arithmetic processor that calculates the output of the A/D converter.

Effects The present invention has the above-described configuration. The second A/D converter can operate with the same power supply voltage, and the second A/D converter can operate on the same power supply voltage, and the second A/D converter can operate on the same power supply voltage, and the first A/D converter can operate on the same power supply voltage. The signals clamped at the upper and lower limits of the input power range of the second A/D converter are respectively output to the first A/D converter. Second A
Since A/D conversion is performed by a /D converter, two A/D converters can be connected in cascade without error, improving bit precision and ensuring reliability against environmental changes.

Embodiment FIG. 1 shows a block diagram of an A/D converter in a first embodiment of the present invention. In FIG. 1, 2 is an adder that adds pulses to the blanking period of the video signal;
3 is a clamp circuit that clamps the pulse part of the output of the adder 2 at the lower limit value vrof1 of the input range of the A/D converters 6 and 7; 4 is a clamp circuit that clamps the pulse part of the output of the adder 2 to the A/D converter 6, 7 is an A/D converter that clamps at the upper limit value vrof2 of the input range, and 6 and 7 have the lower limit value vrof and upper limit value vre f2 of the input range, and use the output signals of the clamp circuits 3 and 4 as input signals. , 8 are arithmetic units that calculate the outputs of the A/D converters 6 and 7, and 9 and 1o are A/D converters 6. Lower limit of input range vrof1 Upper limit vrof2
It is a DC power supply that gives

The operation of the A/D converter of this embodiment configured as described above will be explained using FIG. 2.

9.\-7 When the video signal shown in FIG. 2(a) is input to the adder 2, and the adder 2 adds pulses during the blanking period, the signal shown in FIG. 2(a) is obtained.

Next, in the clamp circuit 3, the pulse portion (in Fig. 2) is clamped to V, resulting in Fig. 2(d), and
In addition, in the clamp circuit 4, the pulse portion of FIG. 2(b) is clamped to vrc, f2, resulting in a signal shown in FIG. 2(C). When the signals shown in FIG. 2 ((1) and (C) are respectively input to A/D converters 6 and 7 and converted to A/D, the video signal higher than the addition pulse potential is input to A/D converter 6, A video signal lower than the addition pulse potential is sent to the A/D converter 7.
The signals are converted into digital signals at , and added at the arithmetic processor 8 to become (n+1)-bit digital signals. This doubles the accuracy of working alone. Moreover, A/D
Since the converter 6 works in the same input voltage range as the A/D converter 7, there is no need to shift the power supply voltage as in the conventional case, and the converter 6 operates stably and the accuracy is improved by the same amount as the theoretical value. Furthermore, since the digital level shift circuits 12 and 13 are not required, the scale of the peripheral circuits is also reduced.

10'. As described above, according to this embodiment, a pulse signal is added to the blanking period of the video signal, and the relative difference between the DC voltages of the video signals input to the two A/D converters is calculated as (vref2').
reft ) by level shifting the two A
/D converters can be connected in cascade without error, the circuit scale is small, the circuit operates stably, and the same accuracy improvement as theoretical can be obtained.

Note that the same reference voltage vref+ is applied to the A/D converters 6 and 7.
and vrof2 are input, but even if different reference voltages are input, the same effect can be obtained with a similar configuration.

In addition, the A/D converter 6. Although we have described the case where the number of end bits is the same, it is clear that cases where the numbers of bits are different can also be realized with the same configuration.

Furthermore, although the case where two A/D converters are used has been described, it goes without saying that a similar configuration can be used in cases where three or more A/D converters are used.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, A/D converters can be connected in cascade without any error, the accuracy can be improved by 11°, -7. Its practical effects are extremely large, especially in fields such as video signals that require high speed and high precision.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an A/D converter according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of the same embodiment, and FIGS. 3 and 4 are diagrams of a conventional A/D converter. The block diagram and FIG. 5 are waveform diagrams showing the operation of the conventional example. 2...Adder, 3, 4...Clamp circuit, 6°...Mom/D converter, 8...Arithmetic circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Diagram (b) ref2 (C) ref I ref2 rdl (d)

Claims (1)

[Claims] an adder that applies a pulse to the blanking period of the video signal; first and second DC power supplies; a first clamp circuit that clamps a pulse portion of the output of the adder to the first DC power supply; a second clamp circuit that clamps the pulse portion of the output of the adder to the second DC power supply; the output of the first clamp circuit is used as an input signal, and the lower limit of the input voltage range is the first DC power supply; a first A/D converter;
A second A/D converter whose input signal is the output of the second clamp circuit and whose upper limit of the input voltage range is the second DC power supply, and output signals of the first and second A/D converters. An A/D converter comprising: an arithmetic processor that performs arithmetic processing.