JPS6358170A - Synchronizing method and circuit therefor - Google Patents

Abstract

PURPOSE:To prevent jitter, by performing operation so that no gate signal is generated by a trigger pulse even when the trigger pulse is applied during a period having possibility generating the jitter. CONSTITUTION:OR circuits 21-24 are connected to the clock input terminals CK1-CK4 of FF11-14 and the output Q1 of FF11 outputs a gate signal which is, in turn, applied to a high speed saw-tooth wave generator/comparator 18 to generate a high speed saw-tooth wave and, when said saw-tooth wave reaches the level of a comparing signal, the second hold-off signal HO2 is generated. By this method, the first hold-off signal HO1 is generated for a definite period and the finish of the second hold-off signal is set to a period longer than the finish period of the signal HO1 by the set-up time of the reset of FF1 or more and delayed by a time shorter than the fastest high speed saw-tooth wave. Therefore, when a trigger pulse P is applied to an input terminal 30 during this period, the set terminal S2 of FF12 is set to 'L' by said trigger pulse P to form a stand-by state and a gate signal is generated by the next pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscilloscope synchronization method and its circuit.

Oscilloscopes need to stably observe various waveforms ranging from low frequencies to high frequencies. For this purpose, a signal that is synchronized with the repetition of the signal under test is required.
Therefore, when the repetition frequency of the observed signal is low, a signal synchronized with each signal is obtained, and when it is high, a signal below a certain repetition frequency synchronized with every few of the repetition signals is jittered. You need to get it without it. Specifically, the present invention relates to an improvement in such a synchronization method and circuit, and in particular to a synchronization method and circuit for a sampling oscilloscope suitable for observing very high frequency signals.

[Prior Art] The circuit configuration of a synchronous circuit used in a conventional sampling oscilloscope will be explained with reference to FIG. 7, and a time chart showing waveforms of each part thereof with reference to FIG.

In FIG. 7, 15 and 16 are both D flip-flops, 25 and 26 are C)R gates, and from the trigger signal applied to the input terminal 30, a gate signal synchronized therewith is sent to the output terminal Q5 of the D flip-flop 15. This signal is applied to a high-speed sawtooth wave generator/comparator 19 to generate a high-speed sawtooth wave, and the comparator compares this with a comparison signal that changes very slowly, such as a staircase wave or a slow sawtooth wave, and generates a high-speed sawtooth wave. A strobe pulse SP is obtained and output at the intersection of the sawtooth wave and the comparison signal.

In FIG. 8, the trigger pulse P applied to the input terminal 30 is shown in (a). (b) shows a high-speed sawtooth wave generated inside the high-speed sawtooth wave generator/comparator 19.

(C) shows the output waveform of the output Q5 of the D flip-flop 15. In (d), after generating a high-speed sawtooth wave in one high-speed sawtooth wave generator/comparator,
A hold-off signal HO is shown which is output to prevent the generator from receiving the gate signal until it has fully recovered. Here, the hold-off signal HO is indicated by the ``H'' level in (d>), and the period of this ``H'' is determined by the circuit constant. In (e), the output Q6 of the D flip-flop 16 is It is shown.

When the up edge of the trigger pulse PO shown in (a) is applied to the input terminal 30, Q5 shown in (C) becomes "H" and the high speed sawtooth wave shown in (b) is generated by the high speed sawtooth wave generator/comparator. 19 occurs and the high-speed sawtooth wave reaches the level of the comparison signal, the hold-off signal HO shown in (d)
is output as ((H+l), the output Q6 of the D flip-flop 16 is set as L fj, and the output (gate signal) 05 of the D flip-flop 15 shown in (C) is set as it L IT. Finish the sawtooth wave.

After that, after a certain period of time (hold-off period) (d
) terminates at “L u ” and is ready to respond to a subsequently applied trigger pulse P1. In such a condition, the up edge of trigger pulse P1 is applied to the clock via OR gate 26. Terminal CK6
When applied to the D flip-flop 16, the hold-off signal applied to its reset terminal R6 is always “L”, and the D@ terminal D6 is always connected to the “H” level. Therefore, Q6 shown in (e) becomes "'H" in response immediately.

The D terminal D5 of the D flip-flop 15 is "H",
Since the hold-off signal HO applied to the reset terminal R5 is L11, the trigger pulse P shown in (a)
When the up edge of 2 is applied to the tarlock terminal CK5 through the OR gate 25, the D flip-flop 15 becomes
Immediately in response, Q5 becomes 1 (H19) and generates the high-speed sawtooth wave shown in (b), and when it reaches the level of the comparison signal, the hold-off signal HO shown in (d) is set to 11 H+1.
which is applied to reset terminals R5 and R6 to reset both D flip-flops 15 and 16, causing their respective outputs Q5 and Q6 to be #L 11. The above operations are repeated.

During the above operation, in Fig. 8(a), the trigger
Pulse P. Even if an equal trigger pulse is applied between P and Pl, the holdoff signal HO shown in (d)
Since the reset terminals R5 and R6 of flip-flops 15 and 16 are reset, another trigger pulse will not cause the gate signal output Q5 to go to (I H+1).

Depending on the trigger pulse P1 applied after that, the gate signal is not output immediately, and the output Q6 is set to 'H' and waits for the application of the next trigger pulse P2. The output Q5, which is the gate signal, does not produce any jitter.Therefore, this circuit is extremely useful when the repetition frequency of the trigger pulse P is high.

However, the repetition frequency of the trigger pulse P is
For example, if the frequency is extremely low, such as 100Hz,
In order to obtain output Q5, which is one gate signal, by trigger pulse P2, trigger pulse P
1, it is necessary for the output Q6 to be set to ``H'', and the repetition frequency of the output Q5, which is the gate signal for this purpose, decreases to 50 mm, which is half of 100 H. In this case, The repetition frequency of the strobe pulse SP output from the high-speed sawtooth wave generator/comparator 19 is also 50H7, and the number of sampling points constituting one screen of the sampling oscilloscope is, for example, 100.
When the point is set to 0, it takes 20 seconds to compose one screen, which is extremely inconvenient when observing signals with extremely low repetition frequencies.

Therefore, when observing a signal with such a low repetition frequency, the repetition frequency of the gate signal should be
A circuit is used that is equal to the repetition frequency of the pulse. This circuit configuration is shown in FIG. 9, and a time chart showing waveforms at each part thereof is shown in FIG. 10, and will be explained. Here, parts corresponding to those shown in FIG. 7 are given the same numbers or symbols.

The difference between the circuit shown in Fig. 9 and the one shown in Fig. 7 is as follows:
Retriggerable one-shot multi-vibration break 17
, the trigger pulse P applied to the input terminal 30 is applied to the up-edge operation input terminal A7, and the output knot Q7 is applied to the set terminal S6 of the D flip-flop. Therefore, the operation of the D flip-flops 15 and 16 is such that the set terminal S6 is t(H+1
The process is the same as shown in FIG. 7 except when .

9 and 10, the input terminal 30 (a)
When the up edge of the trigger pulse Po shown in FIG. Output Q6 is 11
HT! Therefore, the D flip-flop 15 becomes ``H'' immediately, the high-speed sawtooth wave shown in (b) is output, and the output knot Q7 becomes ``L''. When the high-speed sawtooth wave reaches the level of the comparison signal, The hold-off signal HO shown in (d) is output as ((H41), the D flip-flop 16 is reset, and its output Q6 is set to "L",
The output Q5 of the D flip-flop 15 shown in (C) is (I
As L I+, this ends the fast sawtooth wave shown in (b). After that, after a certain period of time (hold-off period) has passed, the hold-off signal shown in (d) becomes “L”.
It becomes D. Now, if the operating cycle of the retriggerable one-shot multivibrator 17 is set to, for example, 100 μs, the output knot Q7 is 11 L l+
The time during which trigger pulse P is not applied after 1
After 00 μs, it changes to tr Hu as shown in (f).

Since this is applied to the set terminal S6 of the D flip-flop 16 to set it, its output Q6 becomes '14 H1
1, and this sets the D input terminal D5 of the D flip-flop 15 to 1 (H+1).This input terminal D5 becomes "'H".
In the transient state where This causes jitter (
The high-speed sawtooth wave shown in b) also causes jitter as shown by diagonal lines. When this high-speed sawtooth wave reaches the level of the comparison signal, it emits a strobe pulse SP and sets the hold-off signal HO shown at (d) to (I H+1
However, this also causes jitter as shown by the diagonal line.

Therefore, the strobe pulse SP also produces jitter.

When the hold-off signal HO becomes ii HI+ (not shown in (d)), the reset terminals R5 and R6 are set to tr Htt, so the D flip-flops 15 and 16 are reset, and their outputs Q5 and Q6 are also output (C) and ( As shown in e), l(L becomes 11) with the jitter shown by diagonal lines.As the output Q5 becomes 11111, (b)
The high-speed sawtooth wave shown in Figure 1 also ends with jitter.

Retriggerable one-shot multi-vibration break 17
The output knot Q7 becomes “L” again when the up edge of trigger pulse P1 is applied, and then 100μ
After s has elapsed (I Htt), the output Q6 becomes 11 Hl!.
When the up-edge of the pulse P2 is applied, as described above, the output Q5 causes jitter, and the high-speed sawtooth wave shown in (b) also causes jitter.

The trigger pulse itself and R2, this output Q6 (I H4
If the output Q5 is applied after the transient state where it goes to 1, the output Q5 will not produce any jitter, and each time the trigger pulse P is applied, a jitter-free fast sawtooth wave can be obtained, thus providing a jitter-free strobe signal. It is possible to obtain pulse SP.

[Problems to be Solved by the Invention] According to the conventional circuit shown in FIG. 9, when the cycle of the trigger pulse P is shorter than the set cycle of the retriggerable one-shot multivibrator, ,
As shown in Figure 8, the output Q is generated by the trigger pulse P1, which is one before the trigger pulse P2 that generates a high-speed sawtooth wave.
If 6 is set to (I HI+ and 1 to rigging pulse P2 is applied, the gate output Q5 is set to tt Htt and a high-speed sawtooth wave is generated (firing) at any time. In other words, the standby state is the state (arming). state), to fire with trigger pulse P2,
I was able to obtain a sick-free gate output Q5 and a high-speed sawtooth wave.

Further, when the repetition period of the trigger pulse P is required to be greater than a certain value, for example, 100 μs, the set terminal S6 is set by the not output Q7 of the retriggerable one-shot multivibrator 17, and the output Q6 is set to 11 Hl+. , each time the trigger pulse P was applied, the same number of jitter-free gate outputs Q5 were obtained, and a high-speed sawtooth wave could be obtained.

However, as explained using FIG. 10, for example, 100 μs has passed since the previous trigger pulse Po, and no trigger pulse P is input during that time. Not output Q7 becomes it HT+, and output Q6 becomes 11 Hl+
When the trigger pulse P, (or P2) is applied in a transient state where the standby state is about to be reached, the gate output Q5 causes jitter, which causes jitter in the high-speed sawtooth wave as well. Ta.

[Means for Solving the Problems] The present invention has been made in order to solve these problems. To this end, first and second hold-off signals are obtained from a high-speed sawtooth generator/comparator, where the first hold-off signal is a hold-off signal for a certain period of time after terminating the high-speed sawtooth wave. -), and the second hold-off signal becomes (I HII) when the fast sawtooth wave reaches the level of the comparison signal, and after a period of time when the first hold-off signal (II Hl!) is 1 ( This is the signal that returns to L+1.

and a first hold-off signal is applied to the reset terminals of the first and second D flip-flops so as to operate similarly to a conventional circuit for a trigger pulse of a predetermined repetition frequency. , 1st
During the period when the hold-off signal is “H”, the gate signal is not output and one of the trigger pulses to obtain the gate signal is output.
The previous pulse changes the output of the second D flip-flop to 11 H! +, and a gate signal is generated by the next applied trigger pulse.

Roughly, third and fourth D flip-flops are provided, a second hold-off signal is applied to each D terminal, and a fourth
The clock input terminal of the D flip-flop has a 1
A pulse is applied, and a gate signal is applied to the reset terminal of the 40th flip-flop, and the output of the 4th D flip-flop and the trigger pulse are applied to the clock input terminal of the 3rd D flip-flop via OR gate 1. and connect the NOT output of the third D flip-flop to the set terminal of the second D flip-flop.1. :
.

[Effect] The first hold-off signal that may cause jitter is
At the time of changing from "H" to "L", the second holdoff is still "H", and when the trigger pulse is applied at this time, if the not output of the 3rd D flip-flop is 11 HII. sets its knot output to 1
11 II, the application of the next trigger pulse brought the device into the standby state, and the subsequent trigger pulse caused it to enter the 71 earring state.

Therefore, in a state that may cause jitter, that is, the first hold-off signal changes from "Hu to L II,"
When a trigger pulse is applied while the second holdoff signal is still at 11811, the standby state is created by the 1~trigger pulse that precedes the trigger pulse that causes firing. No jitter occurs in firing.

[Embodiment] An example of a circuit configuration when the present invention is used in a sampling oscilloscope is shown in FIG. 1, and time charts that are waveform diagrams of each part are shown in FIGS. 2 to 6, and will be described below.

Here, corresponding elements in FIGS. 7 to 10 are shown using the same symbols.

In FIG. 1, 11 to 14 are D flip-flops,
OR circuits 21 to 2 are connected to each clock input terminal CK.
4 is connected, the output Q1 of the D flip-flop 11 outputs a gate signal, which is applied to the high-speed sawtooth wave generator/comparator 18 to generate a high-speed sawtooth wave, and when it reaches the level of the comparison signal, the second The hold-off signal HO2 is set to ``+1'' (prevented from being generated), thereby causing the first hold-off signal HO1 to be generated for a certain period of time and set to ``H'').
, the end of the second hold-off signal HO2 takes longer than the end of the first hold-off signal 1-101 to set up the D flip-flop 11 to the reset terminal (reset terminal R1 becomes 11111, and the clock input terminal CK1
The time until it is possible to obtain a gate signal by inputting to . For example, when FCL 10H131 manufactured by Motorola is used, the setup time is about 1 day. ), and is set to be delayed by a shorter time than the fastest sawtooth wave period (for example, 100 nS).

The reason why the end of the second hold-off signal @H02 is slightly delayed than the end of the first hold-off signal HO1 is because the D flip-flop 11 is reset by the first hold-off signal HO1. This is limited to the time when the first hold-off signal HO1 changes from "H" to """ at the end of the first hold-off signal HO1, and immediately after that. If the end of the off signal HO2 is delayed and a trigger pulse P is applied to the input terminal 30 during this time,
The standby state is created by setting the set heir S2 of the D flip-flop 12 to "L" and using the pulse from 1 to 1 pulse before the trigger pulse to be set.

The operation of the circuit shown in FIG. 1 will be explained below using time charts i shown in FIGS. 2 through 6. In these time charts, (a) shows the trigger pulse P applied to the input terminal 30, and (b) shows the high-speed sawtooth wave generated inside the high-speed sawtooth wave generator/comparator 18 and the comparison signal. (C) shows the output Q1 of the D flip-flop 11 which is the gate signal, (d)
indicates the first holdoff signal, (e) indicates the second holdoff signal, (f) indicates the output Q4 of the D flip-flop 14, (Ca> indicates the not output Q3 of the D flip-flop, and ( h) is the output Q of the D flip-flop
2 is shown.

FIG. 2 shows that the period of the trigger pulse P applied to the input terminal 30 is equal to w of the second hold-off signal HO2 shown in (e).
This shows a case that is sufficiently shorter than the interval J (period in which the signal is "'H").

When the up edge of trigger pulse P1A shown in FIG. 2(a) is applied to input terminal 30, 11 L
The output of the D flip-flop 70 tube 12 shown in (h), which was II, becomes ``H'', and by application of the next up edge of the trigger pulse P2A, the gate output Q1 of the D flip-flop 11 shown in (C> becomes ``H''). , generates a high-speed sawtooth wave shown in (b), resets the reset terminal R4 of the D flip-flop 14, and outputs the output Q shown in (f).
4 becomes 1 (L ++. Output Q1 shown in (C) is OR
Since it is applied to one input terminal of gate 21,
While this output Q1 is l(H++), the up edge of the trigger pulse P3A applied to the other input terminal of this OR gate 21 has no effect on the D flip-flop 11. (b) When the high-speed sawtooth wave reaches the level of the comparison signal, the high-speed sawtooth wave/comparator 18 outputs the second hold-off signal HO2 ('“H++) shown in (e), which is used to trigger the first hold-off signal shown in (d). Start the off signal HO1 (set it to "'H"), set the output Q1 of (C) to "L 91", end the high-speed sawtooth wave of (b), and set the output Q2 shown in (h) to "L ++". .

When the up edge of the trigger pulse P4A shown in (a) is applied to the clock input terminal CK4 of the D flip-flop 14 through the OR gate 24,
The output Q4 shown in (f) becomes "H91."

In this state, even if a subsequent trigger pulse P is applied, the D terminal D1 of the D flip-flop 11 is (h
), the output Q1 never becomes 1 (H++) as shown in (d). However, the first hold-off signal HO shown in (d) determined by the circuit constants
When the period of I ((H+4 ends and becomes 1(L 11), the terminal R2 goes to reset 1 of the D flip-flop 12 (((
Since the reset becomes L11 and the reset is released, when the next input up edge of the trigger pulse PIB shown in (a) is applied to the clock input terminal CK2 via the OR gate 22, the output is immediately responded to. Q2 is (l H+
It becomes +.

In this state, the D terminal D1 of the D flip-flop 11 is "H'', and the first hold-off signal T101
has ended, the reset terminal R1 is (I L I
Since the output Q1 is "L++",
One input terminal of the OR gate 21 remains at 1 (L +1, and if a trigger pulse P2B is applied to the other input terminal 30 of this OR gate 21, the gate signal (Ql becomes ii Hu ), that is, it is in a standby state.

In this way, the next trigger pulse P2B is applied in the standby state created by the trigger pulse PIB, so the D flip-flop 11 operates without jitter and outputs the output Q1 shown in (C). Good output (I H
14) to generate the high-speed sawtooth wave of (b) stably without jitter. The subsequent operation is triggered by the trigger pulse P2.
This is the same as in the case of A''P 4A.

In this way, no jitter occurs if the period of the trigger pulse P is shorter than the period of the second holdoff signal HO2 (period of 11HII).

Next, the trigger pulse P is the first holdoff signal @HO1
The operation in the case where the voltage is applied at the same time as the termination of the voltage will be explained with reference to FIG.

Trigger pulse P shown in FIG. 3(a). When the up edge of is applied to the input terminal 30, the output Q1 of (C)-23= becomes "H11" and outputs the gate signal, and (
Generate the high-speed sawtooth wave shown in b), and when it reaches the comparison voltage, generate the second hold-off signal HO2 (
d H++), which causes the first hold-off signal HO1 shown in (d) to be generated (ll H++), (
Terminate the gate output Q1 shown in C) (44L ++
) and output Q2 to 1 (L++).

After the time determined by the circuit constant, the first hold-off signal HO1 ends (141 IT), and even if the up edge of the trigger pulse P1 shown in (a) is applied at the same time, the D terminal D1 remains at that point. Since it is "L", the D flip-flop 11 does not operate and no gate signal is output, and the output Q1 shown in (C) remains at "L".

At this time, since the set terminal S2 of the D flip-flop 12 is at tV, the output Q2 becomes <I H11. The D flip 70 knob 14 has its D terminal D4 still 'l-' by the second hold-off signal @H○2 as shown in (e).
1", the trigger pulse P1
By applying the up edge of , the output Q4 also becomes 11 H++
becomes. Shortly after that, the second holdoff message @H
O2 shifts to 'L' as shown in (e).

In this state, the reset terminal R1 of the D flip-flop 11 is 11111 as shown in (d), and the D terminal D1 is set to 11111 as shown in (h), and (C)
As shown in , since the output Q1 is 111 ll, if the next trigger pulse P2 is applied to the other input terminal of the OR gate 21 which has this applied to one input terminal, the output Q1 will immediately become " It is in a state in which it is possible to obtain a gate signal, that is, in a standby state.

Since the trigger pulse P2 shown in (a) is applied there, the gate signal is output without jitter (Ql is 11 H
IT). As a result, a high-speed sawtooth wave shown in (b) is output. Reset by this output Q1, the output Q4 shown in (f) becomes 'L''. Here, the D flip knob 13 is DD?i+child D3 is 1rIl as shown in (e), and ( The output Q4 shown in f> is ((
Since it is H++ and is applied to one input terminal of the OR gate 23, the trigger signal applied to the other input terminal is
It is not activated by the up edge of pulse P2, and the output knot Q3 in (g) remains at 1 (L++). When the fast sawtooth wave shown in (b) reaches the level of the comparison signal, the second hold-off signal 1”02 is output as shown in (e) (<I H++), which is
(d) The first hold-off signal @HO1 should be generated.
H91) and reset the output Q2 of (h) to “L”.
), and output Q1 is set to “L” to terminate the gate signal of (C).
') and terminate the high-speed sawtooth wave in (b). The output knot Q3 shown here (CI) remains 4 (Ill) unless it becomes shorter than the period of the trigger pulse P or the period of the second holdoff HO2.

Since it operates in this way, the first holdoff signal HOI
Even if 1~Riga pulse P1 is input at the same time as the end of
As a result, the goo signal cannot be obtained and the standby only creates a state, and since the gate signal is obtained by the next trigger pulse P2, no jitter occurs.

The period of the trigger pulse is long, and the next trigger pulse is
The case where the second hold-off signal HO2 is applied after the end of the second hold-off signal HO2 will be explained using FIG. 4A.

Trigger pulse P shown in FIG. 4A(a). When the up edge is applied, the output Q1 shown in (C) becomes "H", generating the high-speed sawtooth wave shown in (b). When this reaches the level of the comparison signal, the second hold-off signal HO2 in (e) is generated and becomes "H"), and then the first hold-off signal in (d) is set to "H".
The hold-off signal HO1 is generated (44 H11), which causes the gate output Q1 in (c) to be “L++”,
Terminate the high-speed sawtooth wave in (b). (d) first
The hold-off signal HO1 ends (becomes l L ++), and a little later, the second hold-off signal HO2 in (e) also ends (becomes 11111), and then (a)
The up edge of the trigger pulse P1 is input.

At this time, the D terminal D1 of the D flip-flop 11 is (h)
As shown in , since it is 11 L ++, there is no gate signal output. The second holdoff HO2 in (e) is l
(Since L ++, the output knot Q3 of the D flip-flop 13 becomes l(H
Becomes 11. Set by this 'H', (h)
The output Q2 shown in is also 11 H++. In this state, the reset terminal R1 of the D flip-flop 11 is (
As shown in d), since (I L +1) and the output Q1 of (C) is 'L'', the standby state is present.

The up edge of the next trigger pulse P2 shown in (a) is applied there, and the output Q1 in ('C) is jitter-free #
Hu and generates the high-speed sawtooth wave shown in (b), and when it reaches the level of the comparison signal, generates the second hold-off signal H02 shown in (e) (set to 11H++),
It generates the first hold-off signal 1''01 shown in (d>) and terminates the fast sawtooth wave in (b). As shown in (h), the output is "Hto" and the reset terminal R2 is also "H" as shown in (d).
It becomes an undefined (ND) state that can take any value of +.

Even if it becomes "L", if the reset terminal R2 becomes it L H as shown in (d), the set terminal S2 remains "'H", so the output Q2 becomes #H+1.
becomes. Here, the reset legitimate child R1 is it L 11 as shown in (d), and the Q terminal D1 is '' as shown in (h).
Since the output Q1 is 411++ as shown in (C), the D flip-flop 11 is placed in the standby state.

When the period of the trigger pulse after the trigger pulse P2 is applied remains larger than the second holdoff signal HO2, the operation is performed as shown in FIG. 4B.

When the up edge of trigger pulse P3 in (a) is applied after the termination of the second hold-off signal HO2 in (e) generated by trigger pulse P2 (same as +2 in Figure 4A), the D flip float-to 〇 - Since the step 11 is in the standby state, it immediately outputs the gate signal without jitter, and the output Q1 becomes tt H++, generating the high-speed sawtooth wave shown in (b), which is the comparison signal. When the level is reached, the second hold-off signal HO2 shown in (e) should be output (41 H11), (d)
Output the first hold-off signal HO1 shown in 14
H91), which causes the output Q1 to become #L91, terminating the gate signal and also terminating the fast sawtooth wave shown in (b). The first hold-off signal H shown in (d)
When O1 occurs, reset terminal R2 and set terminal S2
and become 44 H91 at the same time, the output Q2 is ((H
+1 or "'L", resulting in an undefined (ND> state), but at the same time as the first hold-off signal HO1 shown in (d) ends (becomes L''), the output Q shown in (h)
2 is determined to be 11 HH, the standby mode is entered, and the operation continues without jitter even in response to the next trigger pulse P4.

The operation in the case where the period of the trigger pulse P changes and becomes shorter and the trigger pulse is applied simultaneously with the end of the first hold-off signal HO1 will be described with reference to FIG.

The first hold-off signal HO1 shown in FIG. 5(d) is generated (becomes "H") by the operation based on the previous trigger pulse Po (not shown) in FIG. The cycle suddenly becomes shorter and HOl ends (
If the trigger pulse P1 in (a) is applied at the same time as ir L u), in order to receive this trigger pulse P1 before the voltage at the reset terminal R1 of the D flip-flop 11 is sufficiently stabilized, Dl level is 11
In the case of H11, the level of 02 is uncertain (ND>, as shown in (h)), and the output Q1 becomes ((H++).

At this time, jitter as shown by diagonal lines in (C) occurs, and the resulting high-speed sawtooth wave shown in (b) also generates jitter as shown by diagonal lines. Until this trigger pulse P1 is applied, D4 of the D flip-flop 14 is (
As shown in e), (I Hl!) and R4 is 'L'' as shown in (C), so the output Q4 becomes 'H'', but as shown in (C) = 31- output Q1 becomes 1 (HP
By becoming I, the reset terminal R4 becomes “H+1”.
The output Q4 is immediately reset to become ii
It is returned to L+1.

When the fast sawtooth wave in (b) reaches the level of the comparison signal, it causes the already finished second hold-off signal HO2 shown in (e) to be generated (it Hrt), which (
Generate the first hold-off signal shown in d) (11H
++), thereby ending the gate output Q1 (<(making it L ll)) and ending the high-speed sawtooth wave shown in (b).

The first hold-off signal HO1 shown in (d) is 1 (H++
Then, since the output knot Q3 is already "'L", the output Q2 shown in (h), which is undefined (ND>), becomes "L".
become.

Termination of the first halt-off signal HO1 shown in (d) resulting from the trigger pulse P1 (HOl becomes ゛['')
Even if trigger pulse P2 is applied at the same time as shown in (a), since Q2 shown in (h) is ii Lu, there is no gate signal output, and output Q4 and output Q2
41 Hfj. That is, since Dl is "H", R1 is "L", and Ql is 1 (L++), the standby state is entered.

In this standby state, trigger pulse P3 is (a)
When applied as shown in , the gate output Q1 without jitter
is set to "HII", thereby generating a high-speed sawtooth wave shown in (b), and resetting the output Q4 to "L".

Eventually, the high-speed sawtooth wave in (b) reaches the level of the comparison signal, causing the second hold-off signal shown in (e) to be generated (
“Hu”, which causes the first hold-off signal HO1 shown in (d) to be generated (makes it 118H), which causes the gate output Q1 shown in (C) to terminate ((makes I L 11), (b) The high-speed sawtooth wave shown in FIG.

The period of the trigger pulse P suddenly changes from a short state to become longer, and the trigger pulse is applied at the timing of the end of the second hold-off signal 1'02. This will be explained with reference to FIG.

When the trigger pulse P1 is applied when the second hold-off signal H02 shown in FIG. 6(e) generated by the trigger pulse Po shown in FIG. 6(a) ends (becomes 11 L 11), Immediately before the application, the output Q2 shown in (h) is "L", so Dl is "L",
Since the gate signal cannot be generated and the D terminals D3 and D4 of the D flip-flops 13 and 14 are either ``Hpa or <l L 14'' and are uncertain, their outputs Q4 and not Q3 are both,(
As shown by the dotted lines in f) and (g), the value is either 1 (H++ or L''). However, since the output Q2 shown in h) is 'H'', the standby state is (R1 is “L”
, Ql becomes "[''), and by applying the next trigger pulse P2, the gate output Q1 shown in (C) is stably obtained without jitter (<(H+1). This is (b)
Generate a high-speed sawtooth wave as shown in It Htj or “
Reset the output Q4 which was L ++ and # L 1
Set it to 1. Here, by applying the trigger pulse P1, the output knot Q3 shown in (g) is changed to ii L T+
Even if it remains as it is, it becomes “HT1” by applying trigger pulse P2. However, this knot Q3 becomes “HT1”.
Whether it is HIT or “L”, the output Q2 shown in (h) is (j HIT, so the gate output Q of (C)
There is no direct relationship to 1.

When the high-speed sawtooth wave shown in (b) reaches the level of the comparison signal, the second hold-off signal shown in (e) is generated.
1''), this is the first holdoff H shown in (d).
O1 is generated (set to "H11"), and the gate output Q1 of (C) is set to "'L" to end), and the high-speed sawtooth wave shown in (b) is ended.

At this time, the reset terminal R2 of the D flip-flop 12
and set terminal S2 are (d) and (q), respectively.
As shown in , the output Q2 becomes 'H', so the output Q2 becomes undefined (ND
>, but the first hold-off signal HO1 shown in (d)
When becomes “LIT,” the output Q2 is determined to be 4 (H+1,
The standby state is (R1 is “L”, Dl is “H”, Q
When the next trigger pulse P3 is applied, the gate output Q1 shown in (C) is generated without jitter, and the above-described operation is repeated.

In the above explanation, the trailing edge of the second hold-off signal H02 only needs to be delayed from the trailing edge of the first hold-off signal 1'01 by, for example, 1 nS or several tens of nanoseconds. It can easily be generated inside the comparator 18.

Since only one input terminal of the OR gate 24 in FIG. 1 is used, it may be omitted and the trigger pulse P may be directly applied to the clock input terminal CK4.

[Effect of the invention] As is clear from the above explanation, according to the present invention,
If a trigger pulse is applied during the period immediately after the first holdoff signal ends that may cause jitter, depending on the trigger pulse, the gate signal may not be generated and the jitter may be suppressed. This prevents the occurrence of this phenomenon, and the present invention has an extremely large effect if used in a high-performance oscilloscope, especially a sampling oscilloscope.

[Brief Description of the Drawings] Fig. 1 is a circuit configuration diagram showing one embodiment of the present invention, Fig. 2, Fig. 3, Fig. 4A, Fig. 4B, Fig. 5, and Fig. 6 are , a time chart when the cycle and timing of the trigger pulse applied to the circuit shown in FIG. 1 are variously changed; FIGS. 7 and 9 are circuit configuration diagrams showing conventional examples; 8 and 10 are time charts of FIG. 7 and FIG. 9, respectively. 11-16...D flip-flop 17...Retriggerable, one-shot, multi-by-break 18.19...High-speed sawtooth wave generator/comparator 21-
26...OR goo 1 30...Input terminal.

Claims (2)

[Claims] (1) A first hold-off signal for generating a gate signal by applying a trigger pulse in a standby state, and further inhibiting the operation for a predetermined period even if a trigger pulse is applied thereafter; A second holdoff signal is generated that ends a little predetermined time later than the end of the first holdoff signal, and the second holdoff signal is generated after the first holdoff signal ends. If a trigger pulse is applied before the synchronization ends, the trigger pulse creates the standby state, and the next pulse generates a gate signal. (2) When the edge of the trigger pulse is applied, a gate signal of the level applied to the D1 terminal is output, and during the period when the gate signal is output, the edge of the trigger pulse applied after that is output. Therefore, the first flip-flop means does not operate and has a reset terminal, and when the edge of the trigger pulse is applied, it outputs a constant level that is constantly applied to the D2 terminal, and during this output period, , a second flip-flop means not actuated by the edge of a trigger pulse applied thereafter and having a set terminal and a reset terminal; and a fourth flip-flop having a reset terminal for outputting the level applied to the D4 terminal by applying the edge of the trigger pulse. means for generating a high-speed sawtooth wave by a gate signal that is an output of the first flip-flop means; a first hold-off signal having a fixed period due to the generation of the high-speed sawtooth wave; and high-speed sawtooth wave generating means for generating a second hold-off signal that ends a predetermined time later than the end, the first hold-off signal is applied to a reset terminal of the first flip-flop means, and the first hold-off signal is applied to the reset terminal of the first flip-flop means, The output of the second flip-flop means is applied to the D1 terminal, the first hold-off signal is applied to the reset terminal of the second flip-flop means, and the not output of the third flip-flop is applied to the set terminal of the second flip-flop means. are connected to each other, and the output of the fourth flip-flop means is applied as the other input of the third flip-flop, and the second hold-off signal is applied to the D3 terminal, and the fourth flip-flop A synchronous circuit characterized in that a gate signal which is an output of the first flip-flop means is applied to the reset terminal, and the second hold-off signal is applied to the D4 terminal.