JPS6357953B2 - - Google Patents
Info
- Publication number
- JPS6357953B2 JPS6357953B2 JP57078852A JP7885282A JPS6357953B2 JP S6357953 B2 JPS6357953 B2 JP S6357953B2 JP 57078852 A JP57078852 A JP 57078852A JP 7885282 A JP7885282 A JP 7885282A JP S6357953 B2 JPS6357953 B2 JP S6357953B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- thin film
- conductive substrate
- semiconductor layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 21
- 239000010408 film Substances 0.000 claims description 17
- 239000010409 thin film Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 description 10
- 229910001220 stainless steel Inorganic materials 0.000 description 5
- 239000010935 stainless steel Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
- H01L31/03921—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
- H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Sustainable Energy (AREA)
- Photovoltaic Devices (AREA)
Description
【発明の詳細な説明】
本発明は薄膜半導体装置における電極形成方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming electrodes in thin film semiconductor devices.
従来の単結晶を用いた半導体デバイスに対し
て、近年はアモルフアスシリコン（以下ａ−Siと
略記）をはじめとする非晶質、微結晶質（マイク
ロクリスタル）または多結晶質を用いた薄膜半導
体デバイスの開発が活発に行われている。このよ
うな非晶質、微結晶質及び多結晶質の半導体デバ
イスは、膜質の抵抗率が大きいため膜の水平方向
への電流の広がりが小さいこと、及び電磁的また
は熱的な手段を利用して結晶化すれば抵抗率が小
さくなる等の特性をもつことが知られている。本
発明はこれらの特性を活用した新規な薄膜半導体
層の電極形成方法を提供するものである。 In contrast to conventional semiconductor devices using single crystals, in recent years thin film semiconductors using amorphous, microcrystalline, or polycrystalline materials such as amorphous silicon (hereinafter abbreviated as a-Si) have been developed. Device development is actively underway. Such amorphous, microcrystalline, and polycrystalline semiconductor devices are characterized by the fact that the resistivity of the film is high, so the spread of current in the horizontal direction of the film is small, and that electromagnetic or thermal means are used. It is known that when crystallized, the resistivity decreases. The present invention provides a novel method for forming electrodes of thin film semiconductor layers that utilizes these characteristics.
まず以下に従来から用いられている薄膜半導体
デバイスとして、ａ−Si太陽電池の構造を説明す
る。 First, the structure of an a-Si solar cell will be explained below as a conventionally used thin film semiconductor device.
第１図に従来のステンレス基板１上に形成され
たｐ−ｉ−ｎ接合アモルフアス太陽電池２の構造
断面図を示す。第１図ａは透明導電膜３で被われ
た受光面側の電極４に対して他方の電気的端子５
を下部、即ち導体基板１側に設けた場合であり、
第１図ｂは物理的または化学的な手段で基板１上
の一部の半導体薄膜を除去して、他方の電極６を
基板１に対して同じ上面側に設けたものである。
第１図ａの構造では他方の電極が基板１の裏面に
位置することになり、半導体デバイスを設置する
場所や配線が著しく制限されるという欠点があ
り、また第１図ｂの構造では半導体層をエツチン
グ除去しなければならず、製造工程が煩雑になつ
たり、受光面が著しく減縮されるという欠点があ
つた。 FIG. 1 shows a structural cross-sectional view of a pin junction amorphous solar cell 2 formed on a conventional stainless steel substrate 1. As shown in FIG. In FIG. 1a, the other electrical terminal 5 is connected to the electrode 4 on the light-receiving surface side covered with the transparent conductive film 3.
is provided at the bottom, that is, on the conductor substrate 1 side,
In FIG. 1B, a part of the semiconductor thin film on the substrate 1 is removed by physical or chemical means, and the other electrode 6 is provided on the same upper surface side as the substrate 1. In FIG.
In the structure shown in FIG. 1a, the other electrode is located on the back surface of the substrate 1, which has the drawback that the location and wiring for installing semiconductor devices are severely restricted.In addition, in the structure shown in FIG. must be removed by etching, which has the drawback of complicating the manufacturing process and significantly reducing the light-receiving surface.
本発明は、従来装置のように配線や設置のため
に制限及び電極形成のために複雑な工程を要する
ことなく、特に半導体層の同一面側からｐ及びｎ
の両電極を導出する構造に適用して効果の著しい
電極形成方法を提供する。 The present invention does not require complicated processes for restricting wiring and installation and forming electrodes unlike conventional devices, and in particular, p and n
The present invention provides a highly effective electrode forming method that can be applied to a structure in which both electrodes are derived.
第２図は本発明による一実施例を示す側面図
で、ステンレス、アルミニウム等の金属基板又は
絶縁体上に導電層を被着した導電性基体１１上に
太陽電池として機能し得るａ−Si１２が積層され
ている。該ａ−Si１２は、ｐ−ｎ、ｐ−ｉ−ｎ、
Ｍ−Ｉ−Ｓ、シヨツトキー等の接合を備え、これ
らの接合が単数又は複数に積層されて、入射光を
受けることにより光起電力を発生する。 FIG. 2 is a side view showing an embodiment of the present invention, in which a-Si 12 that can function as a solar cell is mounted on a conductive substrate 11 in which a conductive layer is deposited on a metal substrate such as stainless steel or aluminum or an insulator. Laminated. The a-Si12 is p-n, p-i-n,
It is provided with junctions such as M-I-S and shot keys, and these junctions are laminated in single or multiple layers and generate photovoltaic force by receiving incident light.
上記ａ−Si１２の表面には出力を取り出すため
の２つの電極、透明電極膜１３及び１５が形成さ
れている。ここで透明電極膜１３はａ−Si１２の
受光面の電極として設けられ、従つて受光面のほ
ぼ大部分を被つて形成されている。一方透明電極
膜１５はａ−Si１２の相対する裏側から出力を取
り出すための電極で、上記透明電極膜１３とは離
れて形成されている。透明電極膜１３及び１５の
夫々には銀ペースト等による端子１４，１６が形
成されている。第３図は上記太陽電池の斜視図で
ある。 Two electrodes, transparent electrode films 13 and 15, for extracting output are formed on the surface of the a-Si 12. Here, the transparent electrode film 13 is provided as an electrode on the light-receiving surface of the a-Si 12, and is therefore formed to cover almost most of the light-receiving surface. On the other hand, the transparent electrode film 15 is an electrode for extracting output from the opposing back side of the a-Si 12, and is formed apart from the transparent electrode film 13. Terminals 14 and 16 made of silver paste or the like are formed on the transparent electrode films 13 and 15, respectively. FIG. 3 is a perspective view of the solar cell.
上記電極端子１６の側についてはａ−Si層１２
の裏面からの出力を導出するため、透明電極膜１
５と基板１１とで挟まれた領域１７の薄膜半導体
層に電気的なパルスを与えて接合を破壊して低抵
抗化し、該低抵抗化された領域に透明電極膜１５
を介して電極端子１６が形成される。 On the side of the electrode terminal 16, the a-Si layer 12
In order to derive the output from the back side of the transparent electrode film 1
An electrical pulse is applied to the thin film semiconductor layer in the region 17 sandwiched between the substrate 11 and the substrate 11 to break the junction and lower the resistance, and a transparent electrode film 15 is applied to the region with reduced resistance.
Electrode terminals 16 are formed via.
上記薄膜半導体層の接合を破壊して低抵抗化す
るため、本発明においては上記のような電気的な
パルスを用いている。次に電気的パルスによる接
合破壊方法を説明する。 In order to destroy the junction of the thin film semiconductor layer and lower the resistance, the present invention uses the electrical pulse as described above. Next, a method of breaking a bond using an electric pulse will be explained.
タンデム型アモルフアス太陽電池は、ステンレ
ス／p1−i1−n1／p2−i2−n2／ITO構造からなり、
各層の膜厚は、p1＝700Å、i1＝4000Å、n1＝150
Å、p2＝150Å、i2＝600Å、n2＝150Å、ITO＝
700Åに作製されている場合を挙げる。上記太陽
電池に、この場合はステンレス基板側をアースに
n2側電極１６を正電圧となる逆バイアスをパルス
状で印加する。第４図ａに示すような印加電圧＋
50V、パルス幅４ｍsecのパルスを１回作用させ
ると領域１７の直列抵抗Rsは第５図Ｂに示すよ
うな分布を示し、また第４図ｂのように逆パルス
−正パルスを対として印加すると第５図Ｃのよう
に抵抗値を減少し、更に上記第４図ｂのパルスを
２回作用させると抵抗値は第５図Ｄのように一層
低い値に分布し、20Ω以下を示した。抵抗値をゼ
ロにすることはできないが、電磁的な手段で１〜
100Ω以下に低下させることができる。 The tandem amorphous solar cell has a stainless steel/p 1 −i 1 −n 1 /p 2 −i 2 −n 2 /ITO structure,
The thickness of each layer is p 1 = 700 Å, i 1 = 4000 Å, n 1 = 150
Å, p 2 = 150 Å, i 2 = 600 Å, n 2 = 150 Å, ITO =
Let us consider the case where the thickness is 700 Å. In this case, connect the stainless steel substrate side to the above solar cell and ground it.
A reverse bias that becomes a positive voltage is applied to the n2 side electrode 16 in a pulsed manner. Applied voltage + as shown in Figure 4a
When a pulse of 50 V and a pulse width of 4 msec is applied once, the series resistance R s in region 17 shows a distribution as shown in Figure 5B, and when a reverse pulse-positive pulse is applied as a pair as shown in Figure 4B. Then, when the resistance value was decreased as shown in Fig. 5C, and the pulse shown in Fig. 4b above was applied twice, the resistance value was distributed to a lower value as shown in Fig. 5D, showing 20Ω or less. . It is not possible to reduce the resistance to zero, but it can be reduced to 1 to 1 using electromagnetic means.
It can be lowered to 100Ω or less.
処で領域１７における抵抗の値が太陽電池の特
性に及ぼす影響を実験した結果を示す。第６図は
面積１cm2のアモルフアスシリコン太陽電池を照度
200ルツクスの蛍光灯下で動作させた時の直列抵
抗の影響を示したものである。 The results of an experiment on the influence of the resistance value in region 17 on the characteristics of the solar cell will now be shown. Figure 6 shows the illuminance of an amorphous silicon solar cell with an area of 1 cm 2 .
This shows the effect of series resistance when operating under 200 lux fluorescent light.
また第７図は直列抵抗と電気的特性の減少率と
の関係を示したものである。第６図及び第７図か
ら読み取れるように直列抵抗の値が100Ωの時、
特性の減少率は２％位であり、この程度の値なら
ほとんど影響がないことが解つた。従つて上記パ
ルス印加によつて得られた20Ω以下の抵抗値は第
６図、第７図に示した100Ω以下であることから、
アモルフアス太陽電池の特性を劣化させないこと
は明らかである。 Further, FIG. 7 shows the relationship between series resistance and the rate of decrease in electrical characteristics. As can be read from Figures 6 and 7, when the series resistance value is 100Ω,
The rate of decrease in characteristics was about 2%, and it was found that a value of this level would have almost no effect. Therefore, since the resistance value of 20Ω or less obtained by the above pulse application is 100Ω or less as shown in FIGS. 6 and 7,
It is clear that the characteristics of the amorphous solar cell are not deteriorated.
上記実施例は基体としてそれ自体が導電体であ
る金属板を用いたが、ガラスのような透光性絶縁
板を用いても構成することができる。 Although the above embodiment uses a metal plate which is itself a conductor as the base, it is also possible to use a light-transmitting insulating plate such as glass.
また基板上に一体的に形成された薄膜半導体層
の複数の電極膜を形成し、該電極膜に上記接合破
壊による低抵抗処理を施こして、各電極間で構成
されるユニツトセル間を直列に接続して構成する
場合にも適用することができる。 In addition, a plurality of electrode films of the thin film semiconductor layer are formed integrally on the substrate, and the electrode films are subjected to the above-described low resistance treatment by breaking the junction, so that the unit cells formed between each electrode are connected in series. It can also be applied to the case of connecting and configuring.
以上本発明によれば、導電性基板上に形成され
た接合を備えた膜の横方向の抵抗の大きい薄膜半
導体層を備えた薄膜半導体装置の、上記半導体層
の導電性基板と接した側に電気的に接続され電極
を形成するに際して、薄膜半導体層の所望部分に
接合に対して少なくとも逆バイアスの電気的なパ
ルス信号を与えることによつて、接合を破壊して
低抵抗領域を形成し、この低抵抗領域上に電極膜
を被着するようになしているため、簡単な方法で
半導体層に接した導電性基板に確実に電気的に接
続された電極を形成することが出来、しかも電極
を設けるための作業を、導電性基板の半導体層の
形成されていない側から行なう必要もなく、また
エツチングによつて半導体層の一部を除去して導
電性基板を露出させて電極を設けたり、あるいは
エツチングによつて半導体層の一部を除去して、
接合を島状に分離して半導体層表面に電極を設け
る必要もなく、同一平面上に電極を簡単に設ける
ことが出来、電極形成の作業性が向上することに
なる。 As described above, according to the present invention, in a thin film semiconductor device including a thin film semiconductor layer having a high resistance in the lateral direction of a film provided with a bond formed on a conductive substrate, the side of the semiconductor layer in contact with the conductive substrate is When electrically connected and forming an electrode, the junction is destroyed and a low resistance region is formed by applying an electrical pulse signal with at least a reverse bias to the junction to a desired portion of the thin film semiconductor layer; Since the electrode film is deposited on this low resistance region, it is possible to easily form an electrode that is reliably electrically connected to the conductive substrate in contact with the semiconductor layer. There is no need to perform the work to provide the conductive substrate from the side on which the semiconductor layer is not formed, and it is also possible to remove a part of the semiconductor layer by etching and expose the conductive substrate to provide the electrode. , or by removing part of the semiconductor layer by etching,
There is no need to separate the junction into islands and provide electrodes on the surface of the semiconductor layer, and the electrodes can be easily provided on the same plane, improving the workability of electrode formation.
第１図ａ，ｂは従来の光応答半導体デバイスの
断面図、第２図は本発明による一実施例の半導体
デバイスの断面図、第３図は同実施例による半導
体デバイスの斜視図、第４図は本発明に適用する
低抵抗化のために印加するパルス波形図、第５図
は印加パルス数と抵抗分布の関係を示す図、第６
図及び第７図はアモルフアス太陽電池の直列抵抗
が特性に及ぼす影響を示す図、
１１：ステンレス基板、１２：ａ−Si、１３，
１５：透明電極、１４，１６：電極端子、１７：
低抵抗領域。
1a and 1b are cross-sectional views of a conventional photoresponsive semiconductor device, FIG. 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 3 is a perspective view of a semiconductor device according to the same embodiment, and FIG. The figure is a pulse waveform diagram applied to reduce resistance applied to the present invention, Figure 5 is a diagram showing the relationship between the number of applied pulses and resistance distribution, and Figure 6 is a diagram showing the relationship between the number of applied pulses and resistance distribution.
Figures 1 and 7 are diagrams showing the influence of series resistance on characteristics of amorphous solar cells, 11: Stainless steel substrate, 12: a-Si, 13,
15: transparent electrode, 14, 16: electrode terminal, 17:
Low resistance area.
Claims (1)
横方向の抵抗の大きい薄膜半導体層の上記導電性
基板と接した側に電気的に接続された電極を形成
する方法において、 上記導電性基板上の薄膜半導体層の一部に、接
合に対して少なくとも逆バイアスの電気的なパル
ス信号を与えて少なくとも該接合を破壊して低抵
抗領域を形成し、 該低抵抗領域上に電極膜を被着して該電極膜を
上記低抵抗領域を介して上記導電性基板に電気的
に接続してなること を特徴とする薄膜半導体装置の電極形成方法。 ２ 前記電気的なパルス信号は正逆両方向からな
る電気的なパルス信号であることを特徴とする特
許請求の範囲第１項記載の薄膜半導体装置の電極
形成方法。[Claims] 1. Forming an electrically connected electrode on the side of a thin film semiconductor layer having a high resistance in the lateral direction of a film provided with a bond formed on a conductive substrate and in contact with the conductive substrate. In the method, applying an electrical pulse signal with at least a reverse bias to a junction to a part of the thin film semiconductor layer on the conductive substrate to destroy at least the junction and forming a low resistance region, the low resistance 1. A method of forming an electrode for a thin film semiconductor device, comprising depositing an electrode film on the region and electrically connecting the electrode film to the conductive substrate via the low resistance region. 2. The method of forming an electrode for a thin film semiconductor device according to claim 1, wherein the electrical pulse signal is an electrical pulse signal in both forward and reverse directions.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57078852A JPS58196061A (en) | 1982-05-10 | 1982-05-10 | Electrode formation for thin film semiconductor device |
| US06/492,675 US4570332A (en) | 1982-05-10 | 1983-05-09 | Method of forming contact to thin film semiconductor device |
| DE19833317108 DE3317108A1 (en) | 1982-05-10 | 1983-05-10 | THIN FILM SEMICONDUCTOR COMPONENT |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57078852A JPS58196061A (en) | 1982-05-10 | 1982-05-10 | Electrode formation for thin film semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58196061A JPS58196061A (en) | 1983-11-15 |
| JPS6357953B2 true JPS6357953B2 (en) | 1988-11-14 |
Family
ID=13673352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57078852A Granted JPS58196061A (en) | 1982-05-10 | 1982-05-10 | Electrode formation for thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58196061A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4697041A (en) * | 1985-02-15 | 1987-09-29 | Teijin Limited | Integrated solar cells |
| JP2632736B2 (en) * | 1990-03-12 | 1997-07-23 | シャープ株式会社 | Thin film semiconductor device |
| FR2795667B1 (en) * | 1999-07-02 | 2001-10-12 | Essilor Int | SMOOTHING TOOL FOR OPTICAL SURFACE, PARTICULARLY FOR OPHTHALMIC LENS |
| DE102007011403A1 (en) | 2007-03-08 | 2008-09-11 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Front side series connected solar module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4856372A (en) * | 1971-11-16 | 1973-08-08 | ||
| JPS5778851A (en) * | 1980-07-03 | 1982-05-17 | Procter & Gamble | Inserting appliance for vagina product |
-
1982
- 1982-05-10 JP JP57078852A patent/JPS58196061A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4856372A (en) * | 1971-11-16 | 1973-08-08 | ||
| JPS5778851A (en) * | 1980-07-03 | 1982-05-17 | Procter & Gamble | Inserting appliance for vagina product |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58196061A (en) | 1983-11-15 |
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