JPS6356923A - High-frequency transistor device - Google Patents

Abstract

PURPOSE:To shorten and equalize the length of a bonding wire, and to improve the characteristics of a transistor by forming a metallic piece in approximately the same thickness as a GaAS chip where adjacent to the chip on a metallized layer and connecting the upper surface of the metallic piece and an electrode for the transistor through wire bonding. CONSTITUTION:Metallic small pieces 7 are bonded onto a metallized layer 3 as a base section 1 for a ceramic package. The material of the metallic small piece 7 consists of the same kovar or oxygen-free copper as a lead, and it may take a quadrilateral, or may take a circle or an ellipse. It is preferable that an area is increased with the object of wire bonding on the upper surface of the metallic small piece and the reduction of inductance, but the area is restricted by a package, chip size, etc. The thickness of the metallic small piece is selected so that height is equalized to a chip. It is desirable that the surface of the metallic small piece is plated previously with gold. The metallic small piece is brazed at the same time as an FET chip is brazed to the package. The same AuSn, AuSi, etc. as the brazing of the FET chip are used as a solder material employed.

Description

[Detailed Description of the Invention] [1 Summary] A small piece of metal is attached to the metallized portion connected to the lead of a puff cage that houses a high-frequency transistor such as a GaAsFET to form a bonding surface at the same height as the FET chip. The structure is such that a bonding wire is used to connect the small metal piece and the GaAs number.

Since the length of the bonding wire is reduced and made uniform, the characteristics of the transistor are improved.

[Industrial application field]

The present invention relates to the structure of a transistor device in which a high frequency transistor such as a GaAsFET is housed in a puff cage, and particularly relates to the structure of a portion connecting between one of the transistors and a lead of the package.

GaAsFETs used in high frequency circuits from several GHz to about 20 GHz are often supplied in a ceramic package with four leads. Since each part constituting a high frequency circuit is usually impedance matched to 50Ω, it is necessary to provide a matching circuit at the input/output section of the FET to achieve impedance matching.

One of the main functions of a matching circuit is to cancel the reflection of the transmitted signal, but if the length of the signal path varies, the phase of the reflected signal will vary, making the design of the matching circuit complicated. Such variations in line length, ie, variations in impedance, are unavoidable to some extent, but it goes without saying that the smaller the range of variation, the easier it is to design a matching circuit.

One of the main causes of variations in input/output impedance of FETs is variation in the length of bonding wires. Wire bonding is performed using a special machine, so extreme non-uniformity does not occur, but as the distance between bonding points increases, differences in wire length and arc shape tend to occur due to variations in chip attachment position, etc. , resulting in variations in its impedance.

Furthermore, the source of the FET is usually grounded, but if its inductance is large, it will reduce the gain of the amplifier circuit. This is because when attempting to suppress the occurrence of feedback via parasitic capacitance between input and output by isolating input and output by completely grounding the source, the smaller the source inductance, the better the isolation effect. It means that it can be enhanced. Here again, it is desirable that the bonding wire length be short.

From the above, shortening the bonding wire greatly contributes to improving the characteristics of the transistor device.

[Conventional technology]

Figure 2a+ (b) shows a conventionally used high-frequency FET package and the state in which the chip is mounted.
It is shown in l. In the same figure (al is a plan view with the lid of the package removed, and in the same figure (bl is a cross-sectional view taken along line XX of the plan view).

The base part 1 of the package is a substantially square ceramic piece with a side of about 1.5 f1, and a metal lead 2 with a radius of about 0.5 n extending in a direction perpendicular to each side is bonded to the bottom surface of the piece through a metallized layer 3. . Kovar is often used for this metal lead, and the metallized layer is a multilayer structure made of, for example, nickel or gold.

This metallized layer extends along the side surface of the ceramic base portion 1 to the upper surface, and the wire 5 is bonded to that portion. The metallized layer connected to the two source leads extending in opposite directions is also continuous on the upper surface of the pedestal. A GaAsFET chip 4 is brazed to the center thereof. The size of the chip is approximately 0.5 dragon squares.

FETs typically have two to three source electrodes, each bonded to the metallization layer with a separate wire to reduce wire inductance. The larger the number of wires, the lower the inductance, but due to area constraints, the number is often 2 to 3.

Furthermore, a ceramic frame 6 is provided around the base, and although not shown, it is sealed with a ceramic plate lid after wire bonding.

[Problem that the invention seeks to solve]

As is clear from the figure, the bonding point on the Qafi,s chip is located at a higher position by the thickness of the chip, and the bonding point on the package side is located at the same height as the surface of the ceramic base. Therefore, this alone increases the wire length by the difference in height, but bonding work on the metallized layer is restricted due to the shape of the bonding head and package, making it even more difficult to shorten the wire length. There is.

In other words, when bonding to the metallized layer, the bonding head must be inserted into the narrow recess between the package frame and the chip, so there is little option to place the bonding point close to the chip. .

Furthermore, it may be necessary to bond to the metallized layer first and then to the chip, contrary to the normal work order, which may reduce the reliability of the connection strength. However, there are still problems with workability.

A known technique that aims to align the height of the top surface of the chip and the surface of the metallized layer is a structure in which a ceramic base is provided with a ridge and the chip is sunk into it. It is not used very often because it is cumbersome and also makes it difficult to braze the chips.

[Means for solving problems]

To facilitate bonding work and reduce wire length,
In the transistor device of the present invention, GaA on the metallized layer
A structure is adopted in which a metal piece having the same thickness as the GaAs chip is provided close to the S chip, and the upper surface of this metal piece and the electrode of the transistor are connected by wire bonding.

[For production]

With the above structure, the length of the bonding wire is reduced to \1/2 compared to a conventional transistor device.

Since the inductance of the newly installed metal piece is minute, the inductance decreases by the amount of wire length shortened.

As the inductance decreases, the gain increases and
Variations in impedance are also reduced, making it easier to create a matching circuit.

〔Example〕

FIG. 1 shows the structure of an embodiment of the present invention. The same figure (al is a plan view of the package with the lid removed, and the same figure (bl)
is a sectional view taken along line XX of the plan view. 1 is a base of the ceramic package, 2 is a lead made of Kovar or the like, 3 is a metallized layer, 4 is an FET chip, 5 is a bonding wire, and 6 is a frame.

The difference from the prior art shown in FIG. 2 is that a small metal piece 7 is bonded onto the metallized layer. The material of the small metal piece 7 is Kovar or oxygen-free copper like the lead, and its dimensions are 0.10 mm thick and 0.1 mm thick on one side as shown in the figure.
．． 2-0.3 am.

The shape may be quadrilateral as shown in the figure, or may be circular or oval.The larger the area is, the better for wire bonding on the top surface and for the purpose of reducing inductance, but it is not suitable for packages or chips. Due to restrictions such as size, the values are as shown above. Further, the thickness is selected so as to match the height with the chip. Furthermore, it is desirable that the surface of the metal piece be plated with gold.

This metal piece is brazed at the same time as the FET chip is brazed to the package. The brazing material used is the same as for brazing the FET chip, such as AuSn, AuSi, etc.

In the above embodiment, the present invention is applied to all of the gate, drain, and source, but the present invention is also effective when applied to only one electrode, and the application location can be selected depending on the situation.

〔Effect of the invention〕

The main effects of the present invention are the following two points.

First, when the present invention is applied to the gate and/or drain leads of FETs, the variation in wire length is reduced,
As a result of the impedance falling within a limited range, matching circuit design becomes easier.

Second, when the present invention is applied to the FET source lead,
The gain increases because the inductance of the ground wire is reduced. For example, in the conventional technology, the source inductance is 0.2
When two wires of +nφ are used, the pH value is about 100 pH, but in the present invention, it decreases to about 50 pH, and is approximately 0.
A gain increase of 5 dB was observed.

These effects appear independently, so if the present invention is applied to all electrodes of the FET, both of the above two effects can be obtained.

Furthermore, as a secondary effect, the surface on which wire bonding is performed becomes higher, and the inconvenience that the bonding head hits the package and becomes an obstacle to the bonding operation is also eliminated.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the structure of the embodiment, and FIG. 2 is a schematic diagram showing the structure of the prior art. In the figure, 1 is a ceramic base, 2 is a metal lead, 3 is a metallized layer, 4 is an FET chip, 5 is a wire, 6 is a frame, and 7 is a small metal piece. 7.っ'Ka Patent Attorney Patent Attorney Sada Igeta-,7,'t-,';V,゛2゛'. X4. Figure 1 Figure 2

Claims (1)

[Claims] A small metal piece is provided in close proximity to the semiconductor piece on which the high-frequency transistor is formed, and is electrically connected to the lead of the package or a conductive part connected to the lead, and whose surface is approximately at the same height as the surface of the semiconductor piece. A high frequency transistor device characterized in that a wire for conductive connection is provided between the upper surface of the metal piece and the surface of the semiconductor piece.