JPS6356863U - - Google Patents
Info
- Publication number
- JPS6356863U JPS6356863U JP15048886U JP15048886U JPS6356863U JP S6356863 U JPS6356863 U JP S6356863U JP 15048886 U JP15048886 U JP 15048886U JP 15048886 U JP15048886 U JP 15048886U JP S6356863 U JPS6356863 U JP S6356863U
- Authority
- JP
- Japan
- Prior art keywords
- level
- analog
- digital converter
- reference level
- imaging output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003384 imaging method Methods 0.000 claims 6
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Facsimile Image Signal Circuits (AREA)
Description
第１図は、この考案の実施例を示すブロツク図
、第２図は、従来例のブロツク図である。
１……撮像素子、４……メモリ、５……ピーク
ホールド回路、６……ＤＡＣ（デイジタル・アナ
ログ変換器）、１１……選択回路、１２……ＡＤ
Ｃ（アナログ・デイジタル変換器）、１３……カ
ウンタ、１４……レベル設定回路。
FIG. 1 is a block diagram showing an embodiment of this invention, and FIG. 2 is a block diagram of a conventional example. 1...Image sensor, 4...Memory, 5...Peak hold circuit, 6...DAC (digital/analog converter), 11...Selection circuit, 12...AD
C (analog-digital converter), 13...counter, 14...level setting circuit.
Claims (1)
出力のピーク値を基準レベルとして、前記撮像出
力をアナログ・デイジタル変換器によりデイジタ
ル信号に変換して記憶し、前記撮像素子による原
稿面の撮像出力を前記々憶内容を基準レベルとし
て、前記アナログ・デイジタル変換器によりデイ
ジタル信号へ変換する画像処理回路において、前
記基準レベルより撮像出力のレベルが低いときに
生ずるレベル判定信号をカウントするカウンタと
、該カウンタのカウント値に応じ逐次低い設定レ
ベルを送出し、前記アナログ・デイジタル変換器
の基準レベルを低下させるレベル設定回路とを設
けたことを特徴とする画像処理回路。 An imaging device captures an image of a reference reflective surface, a peak value of the imaging output is used as a reference level, the imaging output is converted into a digital signal by an analog-to-digital converter and is stored, and the imaging output of the document surface by the imaging device is In an image processing circuit that converts the stored contents into a digital signal using the analog-to-digital converter as a reference level, a counter that counts a level determination signal generated when the level of the imaging output is lower than the reference level; An image processing circuit comprising: a level setting circuit that sequentially sends out a lower setting level in accordance with a count value of , and lowers a reference level of the analog-to-digital converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15048886U JPS6356863U (en) | 1986-09-30 | 1986-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15048886U JPS6356863U (en) | 1986-09-30 | 1986-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6356863U true JPS6356863U (en) | 1988-04-15 |
Family
ID=31066676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15048886U Pending JPS6356863U (en) | 1986-09-30 | 1986-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6356863U (en) |
-
1986
- 1986-09-30 JP JP15048886U patent/JPS6356863U/ja active Pending
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