JPS6355977A - Floating-gate type nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the increase in area of an element, by providing two interconnection layers on the surface of a floating-gate type semiconductor memory device, connecting a source electrode to one interconnection layer, connecting a drain electrode or a gate electrode to the other interconnection layer, taking a roundabout for a propagating path of ultraviolet rays, and using one piece of a signal line for leading out the signal. CONSTITUTION:A memory cell part 1 of a device is surrounded by a source diffused layer 2 other than a part of the memory cell part 1. The cell part 1 is covered with a first interconnection layer 3 through an interlayer insulating film 10. The layers 2 and 3 are contacted. The opening part of the surrounding of the layer 2 is covered with a drain diffused layer 5 at the outside of the layer 2. The surface is covered with a second interconnection layer 6 through a second insulating film 11. A contract 7 is provided to a part of the layer 5. With this part as a drain electrode, the second interconnection layer 6a and the interconnection layer 3 are contacted 8. Thus a source electrode is provided. A signal line 9 of a gate electrode 17 is made to cross the layer 5 and made to pass beneath the interconnection layer 6. The line takes a roundabout for the path of ultraviolet rays.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a floating gate type nonvolatile semiconductor memory device,
In particular, the present invention relates to a floating gate type nonvolatile semiconductor memory device that appropriately prevents a wiring connected to a defective bit from changing from a non-conductive state to a conductive state due to ultraviolet rays.

[Conventional technology]

Conventional floating gate non-volatile semiconductor memory devices, for example, use redundant circuits (defective relief circuits) in which wiring connected to defective bits is rendered non-conductive.This has helped improve the yield of large-scale integrated memory devices. I'm trying. The aforementioned non-conducting state of the wiring is achieved, for example, by passing a large current to cut the polycrystalline silicon wiring or by irradiating it with a laser.

FIG. 4 (al) shows a floating gate type nonvolatile semiconductor memory device having a structure that prevents the device from changing into a conductive state by being erased by ultraviolet rays. enclosure, the upper part of which is connected to the source electrode 1
By covering it with aluminum 04 and making contact 103 with the source diffusion layer 102, the incidence of ultraviolet rays from above and from three sides is blocked. Further, in order to reduce the amount of ultraviolet rays incident from the remaining one side, a gap 107 is formed by separately providing a diffusion layer 105 and making a contact 106 with aluminum.

The signal line 108 of the gate electrode 116 and the signal line 109 of the drain diffusion layer 111 are each formed of polycrystalline silicon wiring, and are drawn out from between the source diffusion layer 102 and the diffusion layer 105 of the cap. Cell part 101
The ultraviolet light that reaches the gap 110 between the source electrode 104 and the aluminum cap 107 and the drain diffusion layer 10
The signal line 109 of 8 enters from the entrance/exit of the signal line 108 of the gate electrode 116 and passes through the silicon oxide film at a distance α.
Limited to things that are propagated.

Naturally, the larger the distance α, the weaker the intensity of the ultraviolet rays when they reach the cell, making it more difficult for the ultraviolet rays to be erased. The distance α can be made as long as the design space allows. It can also bend the path of UV rays. Note that 112 and 115 are silicon oxide films, 113 is an interlayer insulating film, 114 is a floating gate, and 117 is a P-type semiconductor substrate.

[Problem that the invention seeks to solve]

However, in the conventional floating gate nonvolatile semiconductor memory device, the signal line 109 of the drain diffusion layer 111 and the signal line 108 of the gate electrode 116 are drawn out, so it is impossible to completely block ultraviolet rays. However, if an attempt is made to reduce the intensity of ultraviolet light by increasing the propagation distance α of ultraviolet light, there is a disadvantage that the area of the device increases.

[Means for solving problems]

The present invention has been made in view of the above, and in order to prolong cell erasing time by reliably preventing ultraviolet rays from entering the cell portion while suppressing an increase in the device area, two wiring layers are provided on the surface of the device. one wiring layer is connected to the source electrode, the other wiring layer is connected to the drain electrode or gate electrode,
This provides a floating gate type non-volatile semiconductor memory device in which only one signal line is drawn out to the outside.

Hereinafter, a floating gate type nonvolatile semiconductor memory device according to the present invention will be explained in detail.

〔Example〕

FIGS. 1(a), (bl, and c) show an embodiment of the present invention, in which 1 is a cell portion, 2 is a source diffusion layer, 3 is a first wiring layer, and 4 is a source diffusion layer 2 and a first wiring layer. 5 is a drain diffusion layer; 6.6a is a second wiring layer; 7 is a contact that connects the second wiring layer 6 and the drain diffusion layer 5; 8 is a second wiring layer 5; A contact 9 connects the wiring layer 6 and the first wiring layer 3 , and a signal line 9 connects to the gate electrode 17 .

The cell part 1 is surrounded by a source diffusion layer 2 except for a part thereof, and the cell part 1 is covered with a first wiring layer 3 made of polycide, for example, via a first insulating film 10, and the source diffusion layer 2 is Make contact 4 with. Outside the source diffusion layer 2,
The drain diffusion layer 5 surrounds the open part of the source diffusion layer 2, and is covered with a second wiring layer 6 made of, for example, aluminum via the second insulating layer layer 1. Make contact 7 with the department. This becomes the drain electrode. Further, the second wiring layer 6a is connected to the first wiring layer 3 and the contact 8.
is connected to the source electrode. The signal line 9 of the gate electrode 17 crosses over the drain diffusion layer 5,
It passes under the second wiring layer 6. A sectional view taken along the line a-a' of this portion is shown in FIG. 1 (C1).
6a opening, 13 P-type silicon substrate, 14.
16 is a silicon oxide film, and 15 is a floating gate.

As is clear from FIG. 1(b), the second wiring layer 6.6
The ultraviolet rays that entered from the opening 12 between 3
The second insulating film 11 between the wiring layer 3 and the second wiring layer 6
propagates inside, then turns back and connects the first wiring layer 3 and the substrate 13.
Since the light propagates through the insulating film 10 between the two, the journey to reach the cell part 11 becomes long. Further, as is clear from FIG. 1(C), the amount of ultraviolet light incident from the entrance and exit of the signal line 9 of the gate electrode 17 is also smaller than that of the conventional structure having two signal lines.

Therefore, the present invention provides PRO that is difficult to erase by ultraviolet rays.
M cells can be provided. Moreover, the interlayer insulating film 10
．． The effects of the present invention can be further enhanced by using, as 11, an oxide film containing a substance that easily absorbs ultraviolet rays, such as silicon.

FIGS. 2(al), (b), and (C) are process diagrams showing the manufacturing method of the present invention. A part of the surface of the P-type substrate 13 is
A thick silicon dioxide film 14 is formed by the OCO5 method. Next, a polycrystalline silicon layer 15 doped with impurities, which will later become a floating gate electrode, is formed by vapor phase growth or the like, and after buttering, a silicon dioxide film 16 is formed by thermal oxidation. Polycrystalline silicon 117 doped with impurities to become an electrode is formed and buttered (FIG. 2 (al)).Next, for example, arsenic ions are implanted to form an n-type diffusion layer 5, which is to become a drain region. Next, a first interlayer insulating film 10 is formed, and a contact 14 is formed on the source diffusion layer 2, and then a first wiring layer 3 is formed. and then perform buttering (Fig. 2(b)).
After forming the interlayer insulating film 11, a contact 8 is opened on the drain diffusion layer 5 and a part of the first wiring layer 3, and a second
After forming the wiring layer 6 of 6.6, buttering is performed.
b (Figure 2 (C)).

FIG. 3 shows a second embodiment of the present invention, in which 24 is a cell section;
25 is a source diffusion layer, 26 is a first wiring layer, 27 is a contact connecting the source diffusion layer and the first wiring layer 27,
2nd is the drain diffusion layer, 29 is the drain signal extraction wiring, 30 is the drain diffusion layer 2nd and the signal line 29
31 is a gate electrode, 32 is a diffusion layer that connects to the gate electrode, 33.33a is a second wiring layer, and 34 is a diffusion layer 32 that connects the second wiring layer 33 and the gate electrode. A connecting contact 35 is a contact that connects the first wiring layer 26 and the second wiring layer 33.

In this embodiment, the signal line 31 of the gate electrode is connected to the second wiring Ji33, and by using a low resistance material for the signal line 29 of the drain diffusion layer 28, the resistance attached to the drain side can be lowered. There are advantages.

〔Effect of the invention〕

As explained above, according to the floating gate semiconductor memory device of the present invention, two wiring layers are provided on the element surface, one wiring layer is connected to the source electrode, and the other wiring layer is connected to the drain electrode or the gate electrode. As a result, the propagation path of ultraviolet rays is bypassed, and only one signal line is needed to lead out to the outside, thereby suppressing an increase in the element area, more reliably preventing ultraviolet rays from entering the cell area, and extending cell erasing time. be able to.

[Brief explanation of the drawing]

FIG. 1 (al is a plan view of the first embodiment of the present invention, in FIG. 1) is a sectional view taken along the line A-A'' in FIG. 1(a), and FIG. c-c' sectional view, Figure 2 (a) to (C)
3 is a process diagram showing the manufacturing method of the first embodiment of the present invention.
The figure is a sectional view of the second embodiment of the present invention, FIG. 4(a) is a plan view of the conventional embodiment, and FIG. 4 (bl is B in FIG. 4(a)).
-B' sectional view. Explanation of symbols 1124.101--1--Memory cell section 2.2
5.102---- Source diffusion layer 3.26---
-----Drain diffusion layer 4.27------Contacts 6.6a, 33.33a connecting the source diffusion layer and first wiring layer---Part 2 wiring layer 7
---Contact 8.35 for connecting the drain diffusion layer and the second wiring layer --- Contact 9.31.108 for connecting the wiring layer of part 1 and the second wiring layer --- -----Gate signal line 1
0-----First interlayer insulating film 1 t---Second interlayer insulating film 12---
・Second wiring opening 13.117------
・-P type silicon substrate 14.16.112.115-・
-Thermal oxide film 15.114--Floating gate 17.116--Control gate 30.118-
--------・Contact 29.109 connecting the drain diffusion layer and drain signal --- Drain signal line 32 ---
- Diffusion layer 34 connected to the gate electrode - Diffusion layer 3
2 and the second wiring layer.

Claims (1)

[Scope of Claims] A semiconductor comprising a memory cell section consisting of source and drain diffusion layers formed on a semiconductor substrate, and a floating gate electrode and a control gate electrode formed on the semiconductor substrate between the diffusion layers. The storage device has two wiring layers arranged in layers with an interlayer insulating film interposed therebetween to provide a turning point for a propagation path of ultraviolet light, one wiring layer being connected to the source diffusion layer region and the other wiring layer being connected to the source diffusion layer region. A floating gate nonvolatile semiconductor memory device, wherein the wiring layer is connected to the gate electrode or the drain diffusion layer region, and the diffusion layer is formed to surround the memory cell portion.