JPS6355954A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6355954A
JPS6355954A JP19961986A JP19961986A JPS6355954A JP S6355954 A JPS6355954 A JP S6355954A JP 19961986 A JP19961986 A JP 19961986A JP 19961986 A JP19961986 A JP 19961986A JP S6355954 A JPS6355954 A JP S6355954A
Authority
JP
Japan
Prior art keywords
junction
region
pattern
mask
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19961986A
Other languages
Japanese (ja)
Other versions
JPH0770586B2 (en
Inventor
Kazuhiro Obuse
小伏 和宏
Shuichi Kameyama
亀山 周一
Tadanaka Yoneda
米田 忠央
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP19961986A priority Critical patent/JPH0770586B2/en
Publication of JPS6355954A publication Critical patent/JPS6355954A/en
Publication of JPH0770586B2 publication Critical patent/JPH0770586B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To improve electric withstanding voltage and reliability of a P-N junction, by etching a P-N junction forming region at a desired depth with an insulating oxide film as a mask, and thereafter forming the P-N junction. CONSTITUTION:The upper part of a P-type impurity region in a semiconductor substrate 100 is oxidized, to form an oxide film 120. Thereafter a silicon nitride film 130 is deposited. Then, a resist pattern 140 covering a junction forming region is formed. With the pattern 140 as a mask, the nitride film 130 is removed to form a silicon nitride film pattern 130a. With the pattern 130a as a mask, selective oxidation is performed, and oxide films 150a and 150b are formed. Then, the pattern 130a and the film 120 are removed to form a hole on the junction forming region. After the semiconductor substrate surface is exposed, an etching part 10 is formed by isotropic etching with the films 150a and 150b as masks. Then, polysilicon 160 is deposited and N-type impurities are implanted. An N-type impurity region 170 is formed by heat treatment.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するもので、特に集
積回路等のLOCO5法によって分離されたPN接合の
素子分離における電気的耐性を改良した製造方法に係る
ものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing semiconductor devices, and in particular to a manufacturing method that improves electrical resistance in element isolation of PN junctions separated by the LOCO5 method in integrated circuits, etc. This is related.

従来の技術 通常、半導体装置においてPN接合の絶縁分離、例えば
バイポーラICにおけるトランジスタのペース領域とエ
ミッタ領域の電気的絶縁を得るために、半導体基板中の
活性領域周辺をLOCO5法によって選択的に酸化し、
絶縁酸化股領域を形成することが一般的手法になってい
る0例えば第2図(a)に示すように、半導体基板20
0上のP型領域210上にシリコン窒化膜等の耐酸化性
のマスクを残置して選択酸化し、絶!!酸化膜領域25
0a、 250bを形成後、耐酸化性のマスクを除去し
て開口部にN型@域270を形成し、N型領域270を
覆う低抵抗ポリシリコン等の導電材260 e堆積する
BACKGROUND OF THE INVENTION Normally, in order to obtain insulation isolation of a PN junction in a semiconductor device, for example, electrical insulation between a base region and an emitter region of a transistor in a bipolar IC, the periphery of an active region in a semiconductor substrate is selectively oxidized by the LOCO5 method. ,
For example, as shown in FIG.
An oxidation-resistant mask such as a silicon nitride film is left on the P-type region 210 above 0, and selective oxidation is performed. ! Oxide film region 25
After forming 0a and 250b, the oxidation-resistant mask is removed to form an N-type region 270 in the opening, and a conductive material 260e such as low-resistance polysilicon is deposited to cover the N-type region 270.

発明が解決しようとする問題点 第2図(a)に示すような一般的なPN接合の絶縁分離
において、PN接合を分離する絶縁酸化膜領域の先端部
280a、280bは酸化pA厚が薄い上に酸化時の応
力によって膜質が劣化しやすいこと、洗浄、エツチング
等の処理中にtjtJ2図(b)に示すように絶縁酸化
膜領域の先端部280a、280bが後退してPN接合
の短絡が起こりやすいこと、あるいは第2図(c)に示
すようにピンホール290等の発生率が高いことなどの
不安定な要因があり、このためPN接合にサージ等の電
圧が印加された場合絶縁酸化pA領領域先端部280a
、 280bが絶縁破壊を起こしやすい、一方、素子の
微細化に伴って接合の深さを浅くする必要が生じている
。このため絶縁酸化膜領域の先端部280a、 280
bをPN接合の絶縁分離に使用する場合、短絡故障発生
頻度が増加し、製品の歩留および信頼性を低下させてい
た。
Problems to be Solved by the Invention In the insulation isolation of a general PN junction as shown in FIG. The film quality is easily deteriorated by the stress during oxidation, and during processing such as cleaning and etching, the tips 280a and 280b of the insulating oxide film region retreat as shown in Figure (b), causing a short circuit in the PN junction. As shown in Figure 2(c), there are unstable factors such as a high occurrence rate of pinholes 290, etc., and for this reason, when a voltage such as a surge is applied to the PN junction, the insulation oxidation pA Territory area tip 280a
, 280b tends to cause dielectric breakdown. On the other hand, as elements become smaller, it becomes necessary to reduce the depth of the junction. Therefore, the tips 280a, 280 of the insulating oxide film region
When using b for insulation separation of PN junctions, the frequency of short-circuit failures increases, reducing product yield and reliability.

本発明はこのような問題点を解決するもので、PN接合
を絶縁酸化膜領域の先端部から後退させて形成し、PN
接合の電気的耐性の改良と信頼性の改善をする半導体装
置の製造方法を提供するものである。
The present invention solves these problems by forming the PN junction by recessing it from the tip of the insulating oxide film region, and
The present invention provides a method for manufacturing a semiconductor device that improves the electrical resistance and reliability of a junction.

問題点上解決するだめの手段 この問題点を解決するために本発明は、第1導電型の半
導体基板の主面上に耐酸化性の第1のマスク材を形成す
る工程と、前記半導体基板の接合形成予定領域上に前記
耐酸化性の第1のマスク材パターンを選択的に残置させ
る工程と、前記耐酸化性の第1のマスク材パターンをマ
スクと、して選択的に酸化し酸化g!を形成する工程と
、前記酸化膜をマスクとして前記接合形成予定領域を所
望の深さでエツチングする工程と、前記接合形成予定領
域に第2導電型の半導体@域を形成する工程と、前記第
2導電型の半導体領域を覆う導電材を形成する工程とt
−備えた半導体装置の製造方法を提供する。
Means to Solve the Problem In order to solve this problem, the present invention provides a step of forming an oxidation-resistant first mask material on the main surface of a semiconductor substrate of a first conductivity type; selectively leaving the oxidation-resistant first mask material pattern on a region where a bond is to be formed; and selectively oxidizing using the oxidation-resistant first mask material pattern as a mask. g! etching the junction formation region to a desired depth using the oxide film as a mask; forming a second conductivity type semiconductor region in the junction formation region; Steps of forming a conductive material covering the semiconductor region of the second conductivity type;
- A method for manufacturing a semiconductor device is provided.

作用 この方法により、48!l酸化膜領域の先端部の不安定
要因を除くために、PN接合を絶縁酸化膜の先端部から
後退させるべく、この絶縁酸化間をマスクとしてPN接
合形成予定@Hを所望の深さでエツチングしてから、P
N接合を形成することによって、良好なPN接合の絶縁
分離を実現し、高處音高信頼性の半導体装置の提供が可
能となった。
Effect: By this method, 48! l In order to remove the instability factor at the tip of the oxide film region, in order to retreat the PN junction from the tip of the insulating oxide film, the PN junction planned to be formed @H is etched to a desired depth using this insulating oxide gap as a mask. Then, P
By forming the N junction, it is possible to achieve good insulation isolation of the PN junction, and to provide a semiconductor device with high noise and high reliability.

実施例 以下、本発明の製造方法による実施例について第1図(
a)〜(e)に基づき説明する。
Examples Below, examples of the manufacturing method of the present invention are shown in Figure 1 (
The explanation will be based on a) to (e).

(1)まず、半導体基板100中のP型下It物領域上
を酸化して約20OAの醸化JIQ 120を形成した
後、約40OAのシリコン窒化a 130七堆積した。
(1) First, the P-type lower It region in the semiconductor substrate 100 was oxidized to form about 20 OA of JIQ 120, and then about 40 OA of silicon nitride a 130 was deposited.

(2)次いで第1回目のホト・マスク工程によって、接
合形成予定領域上を覆うレジストパターン140を形成
した[第1図(&)]。
(2) Next, a resist pattern 140 was formed to cover the region where a junction was to be formed by a first photomask process [FIG. 1(&)].

(3)次いで、レジストパターン14〇七マスクとして
シリコン窒化jQ130を除去し、シリコン窒化間パタ
ーン130aを形成した[第1図(b)]。
(3) Next, the silicon nitride jQ 130 was removed as a resist pattern 1407 mask to form a silicon nitride interlayer pattern 130a [FIG. 1(b)].

(4)次いで、シリコン窒化膜パターン130♂を、マ
スクとして選択酸化して、約:1OOOAの酸化JE1
150a。
(4) Next, the silicon nitride film pattern 130♂ is selectively oxidized using a mask to oxidize JE1 to approximately 1OOOA.
150a.

+50b t−形成した。[第1fM(c)](5)次
いで、シリコン窒化MJパターン130aおよび酸化7
1120 eウェットエツチング等で除去し前記接合形
成予定領域上に開口を形成して半導体基板面を露出させ
た後、酸化pHQ 150a、 150bをマスク′、
と、して接合形成予定領域の半導体基板面をドライエツ
チング等の等方性エツチングにより約1000Aエツチ
ングしてエツチング部10f:形成した[第1図(d 
) ]。
+50b t-formed. [1st fM(c)] (5) Next, silicon nitride MJ pattern 130a and oxidation 7
1120e After removing by wet etching or the like and forming an opening on the junction formation area to expose the semiconductor substrate surface, oxidized pHQ 150a, 150b is masked',
Then, the surface of the semiconductor substrate in the area where a junction is to be formed is etched by about 1000A by isotropic etching such as dry etching to form an etched portion 10f [see Fig. 1(d)].
) ].

(6)次いで、半導体基板面上に約3000 Aのポリ
シリコン160を堆積した。
(6) Next, polysilicon 160 of about 3000 A was deposited on the semiconductor substrate surface.

(7)次いで、ポリシリコン160中°にN型不純物を
イオン注入した後、熱処理して接合形成予定領域にN型
子II4物領域170を形成した[第1図(e)]。
(7) Next, after ion-implanting N-type impurities into the polysilicon 160, heat treatment was performed to form an N-type element II4 region 170 in the region where a junction was to be formed [FIG. 1(e)].

以上の一連の工程によって、所望するPNIQ合が形成
された。
Through the above series of steps, a desired PNIQ composite was formed.

ただし、他の好ましい製造方法として、(1)工程にお
いて形成するWH酸化性騙は前記のυ化膜とシリコン窒
化膜との多層膜の他、シリコン窒化膜等の単層膜も弯え
ることができる。また(6)工程において形成する導電
關は前記のポリシリコンの他、アルミニューム等の金属
膜やシリコンと金属との化合物等も考えることができる
However, as another preferable manufacturing method, the WH oxidizing layer formed in step (1) can be formed not only from the above-mentioned multilayer film of the oxide film and silicon nitride film, but also from a single layer film such as a silicon nitride film. can. In addition to the above-mentioned polysilicon, a metal film such as aluminum or a compound of silicon and metal may be used as the conductive film formed in step (6).

発明の効果 本発明による製造方法によって、Ae縁酸化頴領域の先
端部の不安定要因が取り除かれ、PN接合にサージ等の
電圧が印加された場合、絶縁破壊による短絡故障発生を
減少させて、PN接合の電気的耐性が改良でき、高歩留
、高信頼性の半導体装置の提供が可能となる。
Effects of the Invention By the manufacturing method according to the present invention, the instability factor at the tip of the Ae edge oxide region is removed, and when a voltage such as a surge is applied to the PN junction, the occurrence of short circuit failure due to dielectric breakdown is reduced. The electrical resistance of the PN junction can be improved, making it possible to provide semiconductor devices with high yield and high reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(e)は、本発明の実施例における製造
方法を示す工程断面図、第2図(a)〜(C)は従来例
を示す断面図である。 100、200・・・半導体基板、110,220・・
・P型不純物領域、120・・・酸化膜、130・・・
シリコン窒化膜、140・・・レジストパターン、15
0,250・・・酸化膜、160゜260・・・ポリシ
リコン、170.270・・・N型不純物領域、280
・・・絶縁酸化膜領域の先端部、290・・・ピンホー
ル。 代理人の氏名 弁理士 中尾敏男 ばか1名第1図 第1図 (C) 12図
FIGS. 1(a) to 1(e) are process cross-sectional views showing a manufacturing method according to an embodiment of the present invention, and FIGS. 2(a) to (C) are cross-sectional views showing a conventional example. 100, 200... semiconductor substrate, 110, 220...
・P-type impurity region, 120... oxide film, 130...
Silicon nitride film, 140...Resist pattern, 15
0,250...Oxide film, 160°260...Polysilicon, 170.270...N type impurity region, 280
. . . tip of insulating oxide film region, 290 . . . pinhole. Name of agent Patent attorney Toshio Nakao One idiot Figure 1 Figure 1 (C) Figure 12

Claims (1)

【特許請求の範囲】[Claims] 第1導電型の半導体基板の主面上に耐酸化性の第1のマ
スク材を形成する工程と、前記半導体基板の接合形成予
定領域上に前記耐酸化性の第1のマスク材パターンを選
択的に残置させる工程と、前記耐酸化性の第1のマスク
材パターンをマスクとして選択的に酸化し酸化膜を形成
する工程と、前記酸化膜をマスクとして前記接合形成予
定領域を所望の深さでエッチングする工程と、前記接合
形成予定領域に第2導電型の半導体領域を形成する工程
と、前記第2導電型の半導体領域を覆う導電材を形成す
る工程とを備えた半導体装置の製造方法。
forming an oxidation-resistant first mask material on a main surface of a first conductivity type semiconductor substrate; and selecting a pattern of the oxidation-resistant first mask material on a region of the semiconductor substrate where a bond is to be formed; a step of selectively oxidizing and forming an oxide film using the oxidation-resistant first mask material pattern as a mask; and a step of forming an oxide film in the region where the junction is to be formed using the oxide film as a mask. A method for manufacturing a semiconductor device, the method comprising: etching in the junction formation region; forming a second conductivity type semiconductor region in the junction formation region; and forming a conductive material covering the second conductivity type semiconductor region. .
JP19961986A 1986-08-26 1986-08-26 Method for manufacturing semiconductor device Expired - Lifetime JPH0770586B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19961986A JPH0770586B2 (en) 1986-08-26 1986-08-26 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19961986A JPH0770586B2 (en) 1986-08-26 1986-08-26 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS6355954A true JPS6355954A (en) 1988-03-10
JPH0770586B2 JPH0770586B2 (en) 1995-07-31

Family

ID=16410862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19961986A Expired - Lifetime JPH0770586B2 (en) 1986-08-26 1986-08-26 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0770586B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04164404A (en) * 1990-10-29 1992-06-10 Ikeda Bussan Co Ltd Movable head rest
US5190707A (en) * 1990-10-30 1993-03-02 Ikeda Bussan Co., Ltd. Method of molding skin-covered foamed article
US6025236A (en) * 1997-02-27 2000-02-15 Micron Technology, Inc. Methods of forming field oxide and active area regions on a semiconductive substrate
US6077735A (en) * 1995-08-31 2000-06-20 Texas Instruments Incorporated Method of manufacturing semiconductor device
US6211046B1 (en) * 1998-07-30 2001-04-03 Sanyo Electric Co., Ltd. Method of manufacturing a semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04164404A (en) * 1990-10-29 1992-06-10 Ikeda Bussan Co Ltd Movable head rest
US5261726A (en) * 1990-10-29 1993-11-16 Ikeda Bussan Co., Ltd. Position adjustable headrest
US5190707A (en) * 1990-10-30 1993-03-02 Ikeda Bussan Co., Ltd. Method of molding skin-covered foamed article
US6077735A (en) * 1995-08-31 2000-06-20 Texas Instruments Incorporated Method of manufacturing semiconductor device
US6025236A (en) * 1997-02-27 2000-02-15 Micron Technology, Inc. Methods of forming field oxide and active area regions on a semiconductive substrate
US6156612A (en) * 1997-02-27 2000-12-05 Micron Technology, Inc. Methods of forming field oxide and active area regions on a semiconductive substrate
US6211046B1 (en) * 1998-07-30 2001-04-03 Sanyo Electric Co., Ltd. Method of manufacturing a semiconductor device

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Publication number Publication date
JPH0770586B2 (en) 1995-07-31

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