JPS6355870B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a solid-state imaging device, and particularly to a solid-state imaging device suitable for obtaining color imaging signals, and a camera using the solid-state imaging device.

(Prior art) Conventionally, when obtaining color imaging signals using one or two solid-state imaging devices with color signals of three or more colors, optical members for color separation such as striped or mosaic color filters have been used. Electrical information corresponding to each color is formed in each pixel by receiving light into the imaging part of the image sensor through the image sensor, and the electrical information of each pixel is read out in time series via a common transfer path. It consists of

FIG. 1 shows an example of a conventionally known solid-state image sensor, and shows a frame transfer type (FT) CCD (Charge Coupled Device).

Reference numeral 1 denotes an imaging section, which is composed of a plurality of pixels for photoelectric conversion arranged along rows and columns. 2
is a memory section, which is a section for storing charge information of each pixel of the imaging section 1, respectively. Reference numeral 3 denotes a horizontal shift register as a transfer path for reading, which takes in information from the memory section 2 one horizontal line at a time and transfers this line information in the horizontal direction to obtain a dot-sequential signal.

Therefore, for example, a striped color filter for color separation as shown in FIG. If the pitch of each pixel of the image pickup unit 1 is matched, the pixels of each column will form a signal corresponding to each color, so that a dot-sequential color signal can be obtained from the horizontal shift register 3.

Each color signal obtained in this manner is converted into, for example, an NTSC signal by a signal processing system as shown in FIG.

That is, the point-sequential imaging output signal output from the CCD amplifier 4 is first sampled and held for each color signal in a signal separation circuit 8 consisting of three sample-and-hold circuits 5 to 7, and then converted into a red signal ER, a green signal EG, and a green signal EG. Separated into blue signal EB. Each color signal ER, EG, EB is variable gain amplifier 9 to 11 respectively.
The level is adjusted and the white balance is controlled. Each level-adjusted color signal is processed in process circuits 12 to 14 including a clamp circuit, a γ correction circuit, an aperture correction circuit, etc., and then converted into a luminance signal and a color difference signal in a matrix circuit 15, and sent to an encoder 16. Therefore, it is converted into, for example, an NTSC signal.

With this configuration, the horizontal shift register 3 will first read out the three primary colors in sequence, so each
To read out on a 3.58MHz carrier
This means that it must be driven with a clock of 3.58MHz x 3 = 10.74MHz, but increasing the clock frequency lowers the transfer efficiency and increases power consumption, so the number of pixels in the horizontal shift register, That is, this has become an obstacle when increasing the number of pixels in the horizontal direction of the imaging section 1.

(Objective) It is an object of the present invention to provide a solid-state imaging device and camera suitable for improved color imaging that can overcome the drawbacks of conventional solid-state imaging devices.

Another object of the present invention is to provide a solid-state imaging device and a camera that can separate color signals well and directly obtain them.

Another object of the present invention is to provide a solid-state imaging device and camera that have less noise, can drive horizontal registers at low speed, and have high transfer efficiency.

(Example) The present invention will be described in detail below based on Examples.

FIG. 4 is a diagram showing an example of the configuration of a solid-state imaging device according to the present invention, in which a color stripe filter for color separation as shown in FIG. 2 is attached to the front surface of the imaging section. 31 to 33 are horizontal shift registers, respectively;
51-53 are horizontal registers 31, 32, 33 for isolating each horizontal register 31, 32, 33 from each other during horizontal charge transfer in the horizontal shift registers 31-33 according to the present invention. 3
A controllable isolation section 17 attached to the memory section 3 is provided between the memory section 2 and the three horizontal shift registers 31 to 33.
By giving a different time difference to each of the three color information included in the last horizontal line, the three color information is distributed and inputted to each of the three horizontal shift registers 31 to 33. a separate input section as a delay means for performing parallel-to-serial conversion;
41 to 43 are charge voltage conversion amplifiers, respectively.

In this way, in this embodiment, three horizontal shift registers 31 to 33 are provided depending on the type of color signal to be obtained as a transfer path for reading, and charges corresponding to each color are transferred to a dedicated horizontal shift register 31. ，
The configuration is such that the input data is divided into 32 and 33 and read out.

Therefore, each color signal is sent to each horizontal register 31, 3.
2,33, and the amplifier 4
Each color signal is separated and outputted from 1, 42, and 43, respectively.

Note that a charge clear drain CD is provided at the lowest end of the image sensor of this embodiment, that is, below the horizontal shift register 31 via an adjacent charge clear gate CL, and a power supply level is connected to the drain CD. has been done.

Next, FIG. 5 shows the electrode configuration of the main part of the image sensor shown in FIG.
The parts up to are shown.

In the diagram, the shaded area is the channel stop, and the CE
31E to 33E are the electrodes of the clear gate CL, 31E to 33E are the transfer electrodes of the horizontal shift registers 31 to 33, respectively, and 51E to 53E are the isolation parts 51 to 53E, respectively.
53 control electrodes, 17E a transfer electrode of the separation input section 17, and 2E a transfer electrode of the memory section 2.
Incidentally, the transfer electrodes 31E, 32E, 33E of each horizontal shift register 31, 32, 33 are formed separately in each horizontal register 31, 32, 33 as shown in the figure, but of course these are made of Al-based, etc. The horizontal registers 31, 32, and 33 are commonly connected by well-known means.

In this embodiment, the configuration is such that the transfer is performed by one phase drive, but this may be 2-phase, 3-phase, or even 4-phase drive.
Even phase is fine.

In the figure, one set of parts indicated by A, B, C, and D constitutes a unit cell, and the potentials of each part of A to D are expressed as P(A) to P(D). Then, P(A)>
A virtual electrode (Virtual Phase) is formed by ion implantation or the like so as to be P(B), and the potential level is fixed. In addition, the potentials of parts C and D under each transmission electrode are set so that P(C)>P(D) is always maintained, and when a low level potential is applied to each electrode, P(A )>P(B)>P(C)>P(D), and when a low level potential is applied, P(C)>P
It is configured so that (D)>P(A)>P(B). Incidentally, if expressed in terms of potential, the relationship is opposite to that of the potentials P(A) to P(D).

Note that _φ1 to _φ3 are clock pulses applied to the electrodes 31E to 33E, and φT is the clock pulse applied to the electrodes 17E, 51E to
Clock pulse applied to 53E and CE, φS
is the clock pulse applied to electrode 2E.

FIGS. 6a and 6b show the clock timing for vertical transfer and the timing for horizontal transfer, respectively.

Further, FIG. 7 is a block diagram schematically showing a color imaging system camera using an embodiment of the image sensor according to the present invention, in which 18 is a driver as a control means, and FIGS. Clock pulses φI, φS, φT, _φ1 to _φ3 as shown in FIG.
Note that φI is a clock pulse applied to the electrode of the imaging section 1. 19 is a reference signal generator. As is clear from the figure, in this configuration, a sample and hold circuit for separating each color information is omitted, resulting in a simple configuration.

Note that the same reference numerals as in FIG. 3 indicate the same circuit elements, and circuits 9 to 16 constitute a signal processing means for forming a video signal.

To explain the operation of the configuration shown in FIG. 5, as shown in FIG. 6a, when charges are vertically transferred from the imaging section 1 to the memory section 2, the vertical synchronizing signal V.
Almost in synchronization with SYNC, clock pulses φI, φS, and φT are used as clock pulses φI, φS, and φT during the period t ₁ to _{t 2} (however, as shown in the figure,
Only the clock pulse φS is slightly ahead of the other clock pulses. ) by supplying at least the same number of vertical pixels as the imaging unit 1,
The charges remaining in the memory section 2 are discarded to the clear drain CD through the isolation sections 51 to 53, the horizontal registers 31 to 33, and the clear gate CL, and the charges in the imaging section 1 are transferred to the memory section 2 and stored therein. Thereafter, as shown in FIG. 6b, from time _t3 onwards, the accumulated charge information in the last row of the memory section 2 is shifted line by line by the clock pulse φs, and the horizontal information is changed by supplying the clock pulse φT as shown. The input is distributed to each of three pixels to the separation input section 17, the isolators 51 to 53, and the three horizontal shift registers 31 to 33, and furthermore, after time _t4 , each horizontal register 3
By applying clock pulses φ ₁ , φ ₂ and φ ₃ to 1, 32 and 33 as shown in the figure, the information is sequentially read out.

Here, in particular, the operation between times t ₃ and _{t 4} , that is, the information of the last one line of the memory section 2 is transmitted to the separated input section 1.
5 and 6 regarding the operation when appropriately distributing and inputting to each of the three horizontal shift registers 31 to 33 through the isolation sections 51 to 53.
This will be explained in detail with reference to FIG. b. For the sake of simplicity, only the movement of charge information in the three columns of the memory unit 2 shown by and in FIG. It goes without saying that each row of the group (group) is evoked at the same time.

First, when the clock pulse φT goes high at time _t3 almost in synchronization with the horizontal synchronization signal H.SYNC,
116, 11 in the last line of memory section 2
The charges accumulated in the portions 7 and 118 move to the portions 111, 114, and 115 in the separate input section 17, respectively, and then this clock pulse φT
When becomes low, these 111, 114, 115
The charges transferred to the parts are 110, 113, and 110, respectively.
Move to the part indicated by 106. Next, when the second clock pulse φT is applied, the electric charge present at the section 106 of the separation input section 17, that is, the charge that was initially accumulated at the section 118 of the column indicated by I in the memory section 2 is changed. The charge is 10 in the isolation section 53.
104 of the horizontal register 33 through the part indicated by 5.
At this time, the electric charges that were present at the portions 111 and 114 of the separation input section 17 are transferred to the portions 108 and 10 through the portions 109 and 112, respectively.
Move to the part indicated by 6. Next, when the third clock pulse φT is applied, the horizontal register 3
3, the electric charge applied to the portion 104 of the horizontal register 3 passes through the portion 103 of the isolated portion 52.
At the same time, the charge in the part 106 of the separation input section 17, that is, the charge that was initially stored in the part 117 in the column shown in the memory part 2, moves to the part 102 in the isolated part 53. 1
10 of the horizontal register 33 through the part indicated by 05.
4, and at this time, the charge that was present at the portion 108 of the separation input section 17 moves through the portion 107 to the portion 106. Then, when the fourth clock pulse φT is applied,
The charge that was in the part 102 of the horizontal register 32 moves to the part shown by 100 of the horizontal register 31 through the part shown by 101 of the isolation section 51,
It is accumulated here, and 1 of the horizontal register 33 is stored.
The electric charge that was on the part 04 passes through the part 103 of the isolation section 52 to the part 102 of the horizontal register 32.
, and is accumulated there, and at this time, the charge that was in the part 106 of the separation input section 17, that is, the charge initially in the column 1 of the memory section 2 shown by
The charge stored in the portion 16 moves to the portion 104 of the horizontal register 33 through the portion 105 of the isolation section 53, and is accumulated there.

As described above, the charges accumulated in the last line of the memory section 2 are distributed to the dedicated horizontal shift registers 31 to 33 for each group of columns, . . . via the separation input section 17. is input. Therefore, for example, if you paste R, G, and B stripe filters so that the column group corresponds to R, the column group to G, and the column group to B, the horizontal register 31 will have R, and the horizontal register 32 will have R, G, and B stripe filters. is G, and charges corresponding to B are accumulated in the horizontal register 33.

After that, after time _t4 , each horizontal register 31, 3
The charges input to the circuits 2 and 33 are read out by applying clock pulses φ ₁ to _{φ 2} , respectively. At this time, since the clock pulse φT is maintained low, the isolation parts 51 to 53 are Each horizontal register 3 functions as a barrier, and therefore each horizontal register 3
When the charges are horizontally transferred in the registers 1, 32, and 33, the mixing of charges between the horizontal registers 31, 32, and 33 can be effectively prevented.

Therefore, when the reading of charges for one horizontal line of the memory section 2 through the horizontal registers 31 to 33 is completed, as shown in FIG. 6b, the memory section 2
A clock pulse φS is applied to the clock pulse φS, and the accumulated charge in each horizontal line is moved vertically by one horizontal line, thereby introducing a new charge into the last line, and then at the above-mentioned time _t3. By performing the operation between t4 and _t4 , the accumulated charges for one new line are distributed and input to the horizontal registers 31 to 33.

By repeating the above operations, the accumulated charges in all lines of the memory section 2 can be read out separately for each color (see OUT in Figure 6b).
1~OUT3).

In the above embodiment, when the input charges are horizontally transferred to the horizontal registers 31 to 33, the phases of the clock pulses φ ₁ , φ ₂ , and φ 3 to each register 31 , 32 , and ₃₃ are adjusted as shown in FIG. 6b. This is done so that the three color signals can be obtained at different phases, but the clock pulse φ ₁
It is also possible to align the phases of ~φ ₃ so that the three color signals are obtained in the same phase, and the method of reading out the three color signals can be arbitrarily selected in relation to the later signal processing. .

Now, in the embodiment described above, the information for one horizontal line of the imaging section 1 is divided into three parts and each part is read out by each of the three horizontal registers 31 to 33. The number of bits constituting each of the horizontal registers 31 to 33 is approximately 1/3 of the number of pixels in the horizontal direction of the imaging section 1. Therefore, the frequency of the clock pulses φ ₁ to _{φ 3} to be applied to each can be reduced to approximately 1/3. 3, which makes it possible to save power, reduce noise, and improve transfer efficiency.In addition, the isolation sections 51 to 53 allow the isolation between each horizontal register 31, 32, and 33 during horizontal charge transfer. This also prevents charge from being mixed in, and a good read signal can be obtained.

In addition, as an example, a frame transfer type
Although we have only mentioned CCDs, it goes without saying that it can be applied to interline CCDs and CPDs (Charge Priming Devices) in exactly the same way.

In addition, the horizontal shift register is used to separately capture and read out charges for each color separated by an optical member for color separation such as a color separation filter, and the color separation filter may be a combination of complementary color filters, etc. It goes without saying that you may also use . Further, instead of a striped color filter, a mosaic color filter may be used.

Also, use two horizontal registers instead of three,
By simply separating the color signals and storing them in each horizontal register, the clock frequency of the clock pulses for the horizontal registers can be halved. Of course, if there are three or more colors separated by the color separation optical member, the number of horizontal registers may be three or more accordingly.

Further, in this embodiment, a clear drain CD and a clear gate CL are provided to clear unnecessary charges, but color information can be separated even without these. Incidentally, the separate input section 17 for the horizontal registers 31 to 33 may be constituted by a gate electrode.

(Effects) According to the solid-state imaging device and camera of the present invention, the sample and hold circuit for separating each color signal is unnecessary or extremely simplified, so the configuration of the signal processing system is simplified, and moreover, when reading out each color information, The problem of mixing between each color information is also sufficiently avoided, making it possible to obtain good color information.
In addition, the readout clock frequency of each horizontal readout section can be significantly reduced, so even if the number of pixels in the horizontal direction in the imaging section is increased, transfer efficiency can be maintained well, and noise can be reduced as well. It has many effects such as power saving.

[Brief explanation of the drawing]

Figure 1 shows the conventional frame transfer type
A configuration diagram of a CCD, FIG. 2 is a diagram showing an example of a striped color filter, FIG. 3 is a diagram showing an example of the configuration of a conventional color imaging signal processing system, and FIG. 4 is a diagram of a solid-state imaging device according to the present invention. Figure 5 showing one embodiment
Figure 4 shows the configuration of the main parts of the element shown in Figure 4, Figures 6a and b are diagrams showing the vertical transfer timing and horizontal transfer timing of the element, respectively, and Figure 7 shows the configuration of a color imaging system using the element. It is a figure showing an example. 1... Imaging section, 2... Memory section, 17... Separation input section, 31-33... Readout section (horizontal shift register), 51-53... Isolation section,
41-43... Output amplifier.

Claims (1)

[Claims] 1. n arranged in the row direction that forms and accumulates electrical information for at least one row by receiving incident light.
(n: an integer) cells, and m rows each having n/m (m is an integer smaller than n) cells for reading electrical information formed in the image storage section. A readout section, an isolation section for selectively separating each readout section, and a predetermined line of electrical information formed by the image storage section.
A delay means is provided between the image pickup storage section and the readout section in order to convert each piece of information into point sequential data and input it to each cell of the readout section, and provides a different time difference for each piece of information on the m cells. and a transfer path for commonly inputting the information of the n cells given different time differences by the delay means to a reading section adjacent to the delay means for each of the m cells; When the information input via the transfer path is sequentially transferred to other readout sections, the isolation section is driven in conjunction with the transfer, and after the transfer to each readout section is completed, the information is transferred from each readout section. A solid-state imaging device comprising: driving means for driving an isolation section to separate each reading section when reading information. 2. An optical system that forms an optical image, and n arranged in the row direction that forms and accumulates at least one line of electrical information corresponding to the optical image formed by the optical system.
(n: an integer) cells, and m rows each having n/m (m is an integer smaller than n) cells for reading electrical information formed in the image storage section. A readout section, an isolation section for selectively separating each readout section, and a predetermined line of electrical information formed by the image storage section.
A delay means is provided between the image pickup storage section and the readout section in order to convert each piece of information into point sequential data and input it to each cell of the readout section, and provides a different time difference for each piece of information on the m cells. and a transfer path for commonly inputting the information of the n cells given different time differences by the delay means to a reading section adjacent to the delay means for each of the m cells; When the information input via the transfer path is sequentially transferred to other readout sections, the isolation section is driven in conjunction with the transfer, and after the transfer to each readout section is completed, the information is transferred from each readout section. a solid-state imaging device having a driving means for driving an isolation section to separate each reading section when reading information; and a signal for forming a video signal using the signals read out through the plurality of reading sections. A camera having processing means.