JPS6355686U - - Google Patents
Info
- Publication number
- JPS6355686U JPS6355686U JP14775186U JP14775186U JPS6355686U JP S6355686 U JPS6355686 U JP S6355686U JP 14775186 U JP14775186 U JP 14775186U JP 14775186 U JP14775186 U JP 14775186U JP S6355686 U JPS6355686 U JP S6355686U
- Authority
- JP
- Japan
- Prior art keywords
- dma
- signal
- period
- request
- processing unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Television Systems (AREA)
Description
第１図は本考案の文字多重放送受信装置の一実
施例を示すブロツク図、第２図は第１図のＤＭＡ
許可パルス発生回路の一例を示すブロツク図、第
３図は第１図の回路動作を説明するタイミング図
、第４図は従来の文字多重放送受信装置を示すブ
ロツク図、第５図は第４図のＤＭＡ要求パルスの
タイミングを説明するタイミング図、第６図は第
４図において擬似的な垂直同期信号を誤検出した
場合のタイミング図である。
１…映像信号入力端子、２…データ取込回路、
３…ＲＡＭ、４…ＲＯＭ、５…ＣＰＵ、６…表示
制御回路、７…画像ＲＡＭ、８…番組選択キーボ
ード、１１…ＤＭＡ許可パルス発生回路、１２…
ＤＭＡゲート回路。
FIG. 1 is a block diagram showing an embodiment of the teletext broadcasting receiving device of the present invention, and FIG. 2 is a DMA shown in FIG. 1.
A block diagram showing an example of a permission pulse generation circuit, FIG. 3 is a timing diagram explaining the circuit operation of FIG. 1, FIG. 4 is a block diagram showing a conventional teletext broadcasting receiver, and FIG. FIG. 6 is a timing diagram illustrating the timing of the DMA request pulse in FIG. 4 when a pseudo vertical synchronization signal is erroneously detected in FIG. 1...Video signal input terminal, 2...Data acquisition circuit,
3...RAM, 4...ROM, 5...CPU, 6...display control circuit, 7...image RAM, 8...program selection keyboard, 11...DMA permission pulse generation circuit, 12...
DMA gate circuit.
Claims (1)
等の文字多重信号を重畳した映像信号をデータ取
込回路にて受信し、データ取込回路はこの映像信
号中の垂直同期信号を基準として検出した文字多
重信号重畳期間に、中央処理装置に対してＤＭＡ
要求を出力し、このＤＭＡ要求期間に基づいて前
記中央処理装置の動作を一時的に中断して前記文
字多重信号をＤＭＡでデータメモリへ書き込む構
成の文字多重放送受信装置において、 垂直同期信号を基準として少なくとも前記文字
多重信号重畳期間を含む一定期間に前記データ取
込回路のＤＭＡ要求を許可するＤＭＡ許可パルス
を発生するＤＭＡ許可パルス発生回路と、 前記ＤＭＡ許可パルスと前記データ取込回路か
ら出力されるＤＭＡ要求パルスとの論理積を得て
、前記中央処理装置へのＤＭＡ要求を行なう論理
積回路とを設けたことを特徴とする文字多重放送
受信装置。[Claim for Utility Model Registration] A data acquisition circuit receives a video signal in which a character multiplex signal such as characters and graphics is superimposed during the vertical retrace period of a television signal, and the data acquisition circuit receives During the character multiplex signal superimposition period detected using the vertical synchronization signal as a reference, DMA is sent to the central processing unit.
In a teletext broadcasting receiving device configured to output a request, temporarily interrupt the operation of the central processing unit based on the DMA request period, and write the teletext multiplex signal to a data memory using DMA, the vertical synchronization signal is used as a reference. a DMA permission pulse generation circuit that generates a DMA permission pulse for permitting a DMA request from the data acquisition circuit during a certain period including at least the character multiplex signal superimposition period; 1. A teletext broadcasting receiving apparatus comprising: an AND circuit for obtaining an AND with a DMA request pulse and issuing a DMA request to the central processing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14775186U JPS6355686U (en) | 1986-09-29 | 1986-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14775186U JPS6355686U (en) | 1986-09-29 | 1986-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6355686U true JPS6355686U (en) | 1988-04-14 |
Family
ID=31061402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14775186U Pending JPS6355686U (en) | 1986-09-29 | 1986-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6355686U (en) |
-
1986
- 1986-09-29 JP JP14775186U patent/JPS6355686U/ja active Pending
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