JPH0264275U - - Google Patents
Info
- Publication number
- JPH0264275U JPH0264275U JP1988144816U JP14481688U JPH0264275U JP H0264275 U JPH0264275 U JP H0264275U JP 1988144816 U JP1988144816 U JP 1988144816U JP 14481688 U JP14481688 U JP 14481688U JP H0264275 U JPH0264275 U JP H0264275U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- stores
- control
- display control
- rom
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Details Of Television Systems (AREA)
Description
第１図は本考案の実施例のブロツクダイアグラ
ム、第２図は従来例のブロツクダイアグラムであ
る。
１１，２１……ＣＰＵ、１２……入出力端子制
御ユニツト、１３，２３……ＲＯＭ、１４，２２
……ＲＡＭ、２４……ＯＳＤ回路、１５，２５…
…バスライン、３０……インターフエース回路。
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 11, 21... CPU, 12... Input/output terminal control unit, 13, 23... ROM, 14, 22
...RAM, 24...OSD circuit, 15, 25...
...Bus line, 30...Interface circuit.
Claims (1)
信号等テレビジヨンの受信映像信号以外の信号を
受け入れる入出力端子制御ユニツトと、該入出力
端子制御ユニツトを制御する第１のＣＰＵと、該
第１のＣＰＵの制御用プログラムを格納する第１
のＲＯＭと上記第１のＣＰＵの制御用データを格
納する第１のＲＡＭと受信映像情報以外の情報を
表示させるための表示制御回路と、該表示制御回
路の制御を行う第２のＣＰＵと、該第２のＣＰＵ
の制御用プログラムを格納する第２のＲＯＭと上
記第２のＣＰＵの制御用データを格納する第２の
ＲＡＭと、上記第１及び第２のＣＰＵを結合する
インターフエース回路より成るテレビジヨン受像
機の表示制御装置。 an input/output terminal control unit that receives signals other than received video signals of the television, such as signals indicating a control state of the television receiver; a first CPU that controls the input/output terminal control unit; The first one stores the control program.
a ROM, a first RAM that stores control data for the first CPU, a display control circuit for displaying information other than the received video information, and a second CPU that controls the display control circuit; the second CPU
A television receiver comprising: a second ROM that stores a control program for the second CPU; a second RAM that stores control data for the second CPU; and an interface circuit that connects the first and second CPUs. display control device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988144816U JPH0264275U (en) | 1988-11-04 | 1988-11-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988144816U JPH0264275U (en) | 1988-11-04 | 1988-11-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0264275U true JPH0264275U (en) | 1990-05-15 |
Family
ID=31412857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988144816U Pending JPH0264275U (en) | 1988-11-04 | 1988-11-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0264275U (en) |
-
1988
- 1988-11-04 JP JP1988144816U patent/JPH0264275U/ja active Pending
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