JPS6355644A - Preventing system for program runaway - Google Patents

Abstract

PURPOSE:To increase the recovery processing speed and also to decrease the service interruption and forcible discontinuation frequencies, by limiting the program breakdown, i.e., a big factor of the program runaway down to a small range between branch instructions. CONSTITUTION:When a branch instruction J2 of an address A6 is carried out and an executing address is equal to A7, this address A7 is stored in a latest branch address register 105. Then an address A3 is obtained and an instruction J3 is extracted. Thus a branch instruction detecting circuit 106 sends an address A8 of the instruction J3 to a branch instruction address comparator 107. Then the comparator 107 gives an access to a branch instruction address memory device 103 to perform comparison. In this case, the address A8 is not stored in the device 103 and the comparator 107 sends an abnormal signal showing discordance to an instruction executing circuit 109 together with a recent normal branch address A9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic switching system using a storage program control method, and particularly to a program runaway prevention method.

[Conventional technology]

Conventionally, in an electronic exchange system using a storage program control method, the fault handling method for preventing program runaway due to program destruction, etc., has a means for detecting abnormal running of the program and a means for reporting the detection result to a central control unit. It is carried out by This conventional method is shown in FIG. 2 below. In the figure, 201 is a central control unit, 202 is a storage device, and 203 is a timer. Central control device 201
The program sequentially executes the programs stored in the storage device 202, and the timer 203 is periodically reset by the program during execution. timer 2
03 is designed to issue an interrupt to the central control unit 201 when it overflows.If the program is normal, it will be reset periodically and no interrupt will occur, but if the program is not reset due to runaway etc. 203 overflows and interrupts the central control unit 201, so runaway can be detected.

[Problem that the invention seeks to solve]

According to the conventional program runaway prevention method described above, it is possible to detect program runaway, but because the runaway is detected by timer overflow, the program that caused the runaway cannot be identified and recovery is required. The only option available is to reload the entire program. As a result, continuity of service could not be maintained, and the interruption time was long.

An object of the present invention is to provide a program runaway prevention method that eliminates the shortcomings of the conventional method of troubleshooting due to program runaway in an electronic exchange system based on the storage program control method, allows the point of runaway occurrence to be identified, and shortens service interruption time. Our goal is to provide the following.

[Failure to solve the problem]

The present invention provides a program runaway prevention method in an electronic exchange system using a storage program control method, which includes a detection means for detecting a program branch point, and data from the program branch point to the branch point detected by the detection means. A data storage means for storing data, a branch instruction address storage means for storing in advance a branch instruction address of a program that describes an exchange process, and a branch instruction address storage means for storing the branch instruction address and the branch instruction address in the branch instruction address storage means when a branch instruction is generated. and a comparison means for comparing the branch instruction address with the branch instruction address stored in the branch instruction address storage means when a branch instruction occurs during program execution.
If there is a mismatch, the program from the previous branch point to the next branch point is loaded from external storage, the old data is returned from the data storage means, and the program starts running from the previous branch point. This feature prevents the program from running out of control and speeds up recovery.

〔Example〕

Next, embodiments of the present invention will be explained in detail using figures.

FIG. 1 is a diagram showing an embodiment of the present invention, in which a storage device 10 in which a program for performing exchange processing is stored.
2, a central control unit 101 that performs exchange processing based on this program, and a storage device 10 that stores branch instructions.
Branch instruction address storage device 10 that stores addresses of 2
3, and a storage device 10 into which data is written in accordance with a write command.
A write data storage device 10 that stores address No. 2 and the data stored at this address, that is, old data.
4, and an external storage device 110 in which the exchange processing program is stored. Central control device 10
1 further includes a latest branch address register 105 that stores the latest branch instruction address, a branch instruction detection circuit 106 that detects a branch instruction, and a branch instruction address storage device 10.
a branch instruction address comparison circuit 107 that compares the branch instruction address stored in the memory device 3 with the branch instruction address from the branch instruction detection circuit 106; a write instruction detection circuit 108 that detects a write instruction; It has an instruction execution circuit 109 that executes various instructions that have been read and also recovers programs and data.

For the sake of explanation, it is assumed that the storage device 102 stores a program as shown in FIG. Here A1-A
9 is an address, J1 to J4 are branch instructions, Wl and W2 are write instructions, and 5l-33 are other instructions. The branch instruction J3 stored at address A8 was originally not a branch instruction, but was changed to branch instruction J3 due to program destruction. The branch instruction address storage device 103 stores addresses A3. A6. A9 is written in advance.

The central control unit 101 sequentially reads instructions from address A1 of the storage device 102 and executes them in the instruction execution circuit 109. The branch instruction detection circuit 106 is connected to the storage device 1
The instruction from 02 is checked, and only if it is a branch instruction, the branch destination address is stored in the latest branch address register 105, but when the program starts executing, the address of the first instruction read is unconditionally stored. It is stored in the latest branch address register 105. When the write command W1 is taken into the central control unit 101 from the next address A2, the write command detection circuit 10 detects this and identifies the address to which data is written by this command and the old data already written to this address. The data is stored in the write data storage device 104. When the branch instruction J1 stored at the next address A3 is input to the central controller 101,
Branch instruction detection circuit 106 detects this and outputs this address A3 to branch instruction address comparison circuit 107. When branch instruction address comparison circuit 107 receives this, it compares it with the address stored in branch instruction address storage device 103 to check whether an address matching address A3 is stored. In this case, since a matching address A3 is found, the branch instruction address comparison circuit 107
determines that this branch instruction is correct, and sends a normal signal indicating this to instruction execution circuit 109. Instruction execution circuit 109
' receives this and executes the branch instruction Jl. Branch instruction J
1 is executed and the branch destination address becomes A4 (assuming that the branch destination address of branch instruction J1 is A4), address A4 is stored in the latest branch address register 105.

At the same time, the contents of the write data storage device 104 are cleared. When the program runs from address A4, the write command W2 at address A5 is detected by the write command detection circuit 108.
As described above, the address accessed by the write command W2 and the contents of that address are stored in the write data storage device 104 as old data. Next, when the branch instruction J2 at address A6 is retrieved, the branch instruction address comparison circuit 107 compares it with the branch instruction address stored in the branch instruction address storage device 103, outputs a normal signal, and continues processing. In this way, if the program stored in the storage device 102 is normal, processing continues.

Next, we will explain what happens when the program is abnormal. Address A
6 branch instruction J2 is executed and the execution address is A7 (
Assume that the branch destination address of branch instruction J2 is A7)
, this address A7 is stored in the latest branch address register 105. Furthermore, as described above, the contents of the write data storage device 104 are cleared.

When the address reaches 88 and the instruction J3 is fetched, since this instruction is a branch instruction, the branch instruction detection circuit 106 converts the address A8 of this instruction to the branch instruction address comparison circuit 107.
Send to. Branch instruction address comparison circuit 107 accesses branch instruction address storage device 103 and performs comparison.

In this case, since the address A8 is not stored in the branch instruction address storage device 103, the branch instruction address comparison circuit 107 uses the abnormal signal indicating mismatch information and the nearest normal branch address A9 to execute the instruction of the central controller 101. Send to circuit 1°9. When the instruction execution circuit 109 receives this mismatch information, it writes the old data to the address that was rewritten before the abnormality was detected, based on the information stored in the write data storage device 104. After the restoration process to the old data is completed,
From the address stored in the latest branch address register 105, the program of normal branch addresses output by the branch instruction address comparison circuit, in this case addresses A7 to A9, is transferred from the external storage device 110 to the storage device 10.
Load into 2.

After the loading is completed, the program starts running using the address A7 stored in the latest branch address register 105 as the starting address.

〔Effect of the invention〕

As explained above, the present invention has the effect that by limiting program destruction, which is a major cause of program runaway, to a small range between branch instructions, recovery processing can be performed quickly, and service interruptions and forced disconnections can be reduced. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional program runaway prevention system. 101, 201...Central control unit 102, 202...Storage device 103...Branch instruction address storage device 104
...Write data storage device 105...
-Latest branch address register 106...Branch instruction detection circuit 107...Branch instruction address comparison circuit 108...Write instruction detection circuit 109
...Instruction execution circuit 110 ...External storage device 203 ...Timer

Claims (1)

[Claims] (1) In a program runaway prevention method in an electronic switching system using a storage program control method, a detection means for detecting a program branch point and data stored from the program branch point detected by the detection means to the branch point are stored. a branch instruction address storage means for storing in advance a branch instruction address of a program that describes an exchange process; and a branch instruction address storage means for storing in advance a branch instruction address of a program that describes an exchange process; and comparing means for comparing the branch instruction address stored in the branch instruction address storage means when a branch instruction occurs during program execution, and when there is a mismatch, the branch instruction address is compared with the branch instruction address stored in the branch instruction address storage means. Loads the program from the previous branch point to the next branch point from external storage, returns the old data from the data storage means, and starts running from the previous branch point, thereby preventing program runaway and recovery. A program runaway prevention method that is characterized by rapid execution.