JPH02245937A - Information processor - Google Patents

Abstract

PURPOSE:To detect the destruction of a new PSW area and take a proper countermeasure by comparing the value of a read new PSW with the value in a new PSW holding means and indicating the destruction of the new PSW area by interruption when a dissidence between both the values is detected. CONSTITUTION:A new PSW area holding means 20 which holds the correct value of the new PSW area 18 present on a main storage 14 fixedly is provided and the same value with the new PSW area 18 on the main storage 14 is stored in the new PSW area holding means 20 with a specific data set instruction. Then, if the value in the PSW area 18 is destroyed owing to a bug of an OS program due to the insufficient protection of the new PSW area 18 on the main storage device 14, the value of the new PSW which is read out by interruption processing is compared with the correct value held in the new PSW area holding means 20. Thus, the destruction is detected and an error is indicated by the interruption. Consequently, the abnormality due to the destruction of the new PSW area 18 on the main storage 14 is detected to take the proper countermeasure speedily.

Description

[Detailed description of the invention] [Required e1] Regarding an information processing device in which protection measures are taken for a new PSW area on main memory used during interrupt operation, it is possible to detect destruction of the new PSW area and take appropriate countermeasures. With the purpose of The value read from the new PSW area holding means is compared with the value of the new PSW area holding means, and if the two do not match, a destruction notification of the analyzed PSW area is generated by an interrupt.

[Industrial Application Field] The present invention is directed to a new PS on the main memory used during interrupt operation.
The present invention relates to an information processing device that takes protection measures for the W area.

The protection of the main storage area in an information processing device is performed by access management based on a combination of a ring number specified by a PSW (Program Status Word) and a ring number assigned to each segment.
Since the FrPSW area on main memory, which is read as the current PSW value of the CPU when an interrupt factor occurs in J, is in segment units, protection by ring numbers is insufficient, and an error in the OS program may occur. There is still a possibility that the new PSW area will be destroyed, and countermeasures against destruction of the new PSW area are required.

[Prior Art] FIG. 3 is a block diagram of a conventional device showing processing when an interrupt factor occurs in the CPU.

In Figure 3, first, the interrupt function of the information processing device is
This is a function that changes the state of the CPU depending on the internal or external conditions of the system or the conditions of the CPU 10 itself.In order to quickly and efficiently respond to high-priority interrupt conditions, CPU10 interrupts are input/output interrupts, program interrupts, and They are classified into four types: visor call interrupts and machine interrupts.

When such an interrupt factor occurs and the CPU 10 is in a state where it can accept the interrupt factor, the interrupt operation is performed according to the following order.

■CPLJ10 uses the current PSWI 2 as the old PSWI in the main memory 14.
It is saved by storing it in the SW area 16 as an old PSW. The old PSW area 16 stores the next instruction address of the interrupted instruction and a code indicating the cause of the interruption.

■Next, the CPU inputs additional information 24 associated with the interrupt.
The information is stored in the additional information storage area 26 on the top of 4.

(2) Next, the CPU 10 reads the value existing in the new PSW area 1B on the main memory 14 and stores it as the current PSW 12. Subsequently, the CPU 10 shifts to processing defined by the new PSW value read out as the current PSWI 2.

By the way, protection of the area on the main memory in an information processing device that performs such interrupt operations has conventionally been performed according to access management based on a combination of a ring number specified by the PSW and a ring number assigned to each segment. There is.

[Problem to be Solved by the Invention] However, in protecting the main storage area of such a conventional information processing device, the main storage area to be protected by the ring number is segment-based.
It is not suitable for protection of a limited range like the SW area 18, that is, for controlling access prohibition and permission.

For this reason, the data stored in the IPSW area 1B by the data set command during the initial program routine (IPL) is
There is still a possibility that it may be destroyed due to a bug in the OS program, and the corrupted FrPSW will be used at the time of an interrupt to cause abnormal operation, which in the worst case will lead to system down, and the cause of the abnormality. The problem was that it was extremely difficult to understand.

The present invention has been made in view of such conventional problems, and provides an information processing device that can detect an abnormality due to destruction of a new PSW area on main memory and quickly take appropriate countermeasures. The purpose is to

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, first of all, the present invention is configured such that when a predetermined interrupt cause occurs in the CPU 10, the specified PSWI on the CPLJ 10
2 to the old PSW area [16 on the main memory 14, and read the value of the FrPSW area 18 on the main memory 14 and save it to the old PSW area [16] on the main memory 14.
The target is an information processing device that performs an interrupt operation as the current PSW 12 of a PU.

In the present invention, for such an information processing apparatus, a new PSW area holding means 20 is provided to fixedly hold the correct value of the new PSW area 18 existing on the main memory 14, and the correct value of the new PSW area 18 existing on the main memory 14 is provided. The same value as the new PSW area 18 on the main memory 14 is stored in the new PSW area holding means 20, and the CPU
10, when an interrupt factor occurs and the value of the new PSW area 18 on the main memory 14 is read, the comparing means 22 compares the successively read new PSW value and the value of the new PSW holding means 20, The configuration is such that when a mismatch between the two is detected, a notification indicating the destruction of the new PSW area 18 is generated by an interrupt.

In addition, the command to set data in the new PSW area holding means 20 is an command that can be executed only by firmware.
The contents of the new PSW area holding means 20 are prevented from being destroyed by the OS program.

[Function] In the information processing device of the present invention having such a configuration, the new PSW may be lost due to a bug in the OS program due to insufficient protection of the new PSW area on the main storage device.
If the value of the area is destroyed, the destruction is detected by comparing the new PSW value read by the interrupt operation with the correct value held in the analysis PSW area holding means, and an error notification is performed by the interrupt. .

Therefore, self-contradictions within the OS level can be detected at an early stage to prevent a system down or to efficiently identify a location causing a self-contradiction within the OS level, thereby making it possible to modify the OS program at an early stage.

[Embodiment] FIG. 2 is a block diagram showing an embodiment of the present invention.

In FIG. 2, 10 is a CPU, and 14 is a main storage device. The main storage device 14 is provided with an old PSW area 16, an analysis PSW area 18, and an additional information storage area 26. Old P
Each of the SW area 16 and the new PSW area 18 is composed of four areas: machine interrupts, supervisor interrupts, program interrupts, and input/output interrupts. In the new PSW area 18, the OS program normally sets a predetermined value for the system during IPL.

In addition, when an interrupt factor occurs in CPLJIO, the contents of the current PSWI 2 of the CPU 10 are transferred to the old PSW area 1 in accordance with the interrupt factor on the main storage device 14 by hardware.
*Ji P S in response to the same interrupt factor.
The value of the W area 18 is loaded as the current PSW 12 of the CPU 10. Here, the 8 values of the new PSW area 18 loaded by the OS program at the time of IPL store information such as whether or not the mode is privileged, whether or not the address is to be changed, interrupt mask, ring number, instruction address, etc. ing.

Such a configuration is the same as the conventional one, but in addition, in the present invention, the frP existing on the main storage device 14
In order to detect the destruction of the SW area 18, the CB area 100
Newly established.

That is, the CB area 100 is provided with a new PSW area holding means 20, and the new PSW area holding means 20 has a
The new PSW area 1 of the main storage device 14 is created by the OS program.
The same value as the analysis PSW value for 8 is loaded.

Here, in order to prevent the correct value loaded into the new PSW area holding means 20 from being changed by the OS program, the new PSW area 18 of the main memory @ 14 is rewritten by O8 and by firmware. However, the new PSW holding means 20 can be rewritten only by firmware,
Rewriting by OS program is not possible.

Furthermore, the CB area 100 is provided with a comparing means 22, and the comparing means 22 reads the IJ'i P corresponding to the interrupt factor as the value read from the \JrPSW area 18 of the main storage device 14 in response to the interrupt factor. SW area holding means 20
Compare the values with and when the two match, output H level,
When there is a mismatch, an L level output is produced. The output of the comparison means 22 is inverted by an inverter 30, and the output of the comparison means 22 is inverted by an inverter 30.
The L level output when a mismatch is detected is inverted and set to H level, and the H level output of this inverter 30 causes the I
An error interrupt is generated to notify the destruction of the J''rPSW area 18.

Next, the operation of the embodiment shown in FIG. 2 will be explained.

First, when IPLing the system, analyze the main memory @14 ps
Analytical PSW holding means 20 for w region 18 and CB region 100
The OS program sets predetermined values in the system for each of machine interrupts, supervisor interrupts, program interrupts, and input/output interrupts, and starts processing operations.

If an interrupt factor such as a machine interrupt, supervisor interrupt, program interrupt, or input/output interrupt occurs to the CPU 10 during processing, the CPU 1
The contents of the current PSW 12 of 0 are stored in the old PSW area] 6 corresponding to the interrupt factor on the main storage device 14 as shown in (3). Subsequently, the CPU 10 stores the additional information 24 in the main storage device 14.
It is stored in the upper additional information storage area 26 as shown in ■.

Next, the value of the new PSW area 18 on the main storage device 14 according to the interrupt factor is read by the hardware, and the CP
It is loaded into U10 as a flat PSW12 as shown in ■.

At this time, the value read from the new PSW area 18 of the main storage device 14 is set to the comparing means 22 provided in the CB area 100, and at the same time, the value of the new PSW area holding means 20 corresponding to the interrupt factor is set. , the comparison means 22 compares the two, and if they match, the output of the inverter 30 becomes L level, no error interrupt is generated, and the CP
U10 shifts to the process defined by the new PSW as the current PSW12.

On the other hand, if the new PSW area 18 on the main memory 14 is accidentally written to and the contents have changed due to a bug in the OS program, the comparison means 22 detects a mismatch and the inverter 30 The output becomes H level to generate an error interrupt, and in response to the error interrupt, appropriate measures such as outputting a message notifying destruction of the new PSW area 1B, history rotation, and system stop are performed.

Of course, even if an attempt is made to replace the area including the new PSW area in the main storage device 14 by mistake due to a bug in a user program such as an application, there will be no problem since it is protected by hardware features such as ring numbers and limit registers. There isn't.

[Effects of the Invention] As explained above, according to the present invention, even if the new PSW area of the main memory is destroyed due to a bug in the OS program, the correct value can be restored when moving to processing using the destroyed analysis PSW. Since destruction is detected and an error interrupt is generated by comparison with the new PSW, it is possible to prevent abnormal processing and system down due to execution of a new destroyed PSW, and prevent system down by knowing abnormalities within the OS level. , or O
It becomes possible to easily discover the location where self-contradiction occurs within the S level, and it is possible to eliminate early correction of the OS program.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention; FIG. 2 is a configuration diagram of an embodiment of the present invention; FIG. 3 is a block diagram of a conventional device. In the figure, P.U. Current PSW main storage Old PSW area New PSW area Analysis PSW pirate retention means means of comparison Additional information 26: Additional information storage area 30: Inverter 100: CB territory Kashizumemi of the area intake Figure 3

Claims (2)

[Claims] (1) When a predetermined interrupt factor occurs in the CPU (10), the current PSW (12) on the CPU (10) is stored in the main memory (
14) Information processing that saves to the old PSW area (16) above, reads the value of the new PSW area (18) on the main memory (14), and performs an interrupt operation as the current PSW (12) of the CPU (10). The device is provided with new PSW area holding means (20) for fixedly holding the correct value of the new PSW area (18) on the main memory (14), and the new PSW holding area (20) is ) to the new PS on main memory (14)
The same value as the W area (18) is stored, and when an interrupt cause occurs in the CPU (10), the value read from the new PSW area (18) of the main memory (14) and the new PSW area holding means ( 20) using the comparison means (
22), and if a discrepancy is detected, the new PS
An information processing device characterized in that a destruction notification of a W area (18) is generated by an interrupt. (2) In the information processing device according to claim 1, the new P
An information processing device characterized in that an instruction to set data in SW area holding means (20) is an instruction that can be executed only by firmware.