JPS635563A - High breakdown strength semiconductor device - Google Patents

Abstract

PURPOSE:To relieve electric field strength, and to contrive to enhance the breakdown strangth of a semiconductor device by a method wherein platinum is introduced at least to the interface between the surface of a substrate and a silicon dioxide film in the breakdown strength constructing region in the neighborhood of P-N junction. CONSTITUTION:A high withstand voltage semiconductor device is constructed of a high resistance N-type semiconductor layer (collector) 1, a P-type semiconductor layer (base) 2, guard rings 3, an N-type semiconductor layer (emitter) 4, a high concentration N-type semiconductor layer 5, channel stopper regions 6, platinum diffusion regions 7, oxide films (SiO2 films) 8, electrodes 9 and depletion layers 10. At this time, contact holes are opened on the surfaces of the guard rings 3, and platinum is diffused only to the breakdown strength parts from the hole parts thereof. Accordingly by making interfacial charge of Si-SiO2 to be negative, a transistor having a high breakdown strength and a large amplification factor can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to increasing the breakdown voltage of Brenner type semiconductor devices such as diodes and transistors. Planar semiconductor devices are stabilized by covering the main P-N junction exposed on the surface of the semiconductor substrate with a silicon oxide film (hereinafter referred to as 5ins). For high voltage products, 8i 810 has a fixed charge at the interface and positive ions in the film, which makes it difficult for air 2N4 on the surface to spread, especially with N-type silicon bars and bars, resulting in high electric field strength. This is a deterrent factor. For this reason, conventionally, a so-called guard ring structure has been constructed using a field plate structure to reduce the electric field strength and increase the withstand voltage. However, even with such a structure, the breakdown voltage is at most 70% to 80% of the theoretical value, which is not sufficient.

Therefore, in order to get closer to the theoretical value, for example, guard ring junction (
If the annular area) is increased, the area of the voltage-resistant part increases, the chip size becomes larger, and the cost of the chip increases.
The present invention eliminates such drawbacks and provides an economical and high-voltage planar semiconductor device, which changes the interfacial charge in the film from positive to negative, which is commonly found in products using a 5ift film as a protective film. This makes it possible to achieve high voltage resistance. FIG. 1 shows an embodiment of the transistor of the present invention, in which 1 is a high-resistance N-type semiconductor (collector), 2 is a P-type semiconductor (base), 3 is a guard ring, 4 is an NW semiconductor (EM, RI), 5 is a high concentration N-type semiconductor, 6 is a channel strike,
7 is a platinum diffusion region, 8 is an oxide film (StO,), 9 is an electrode, and 10 is a depletion layer. However, Applicant Hihara et al. first filed Article 810. By mixing platinum near the interface between +81 and the silicon substrate 2, the charge at the interface is changed from positive to negative, thereby proposing a semiconductor device that can achieve a high breakdown voltage. That is, Fig. 2 is a characteristic diagram showing the relationship between the platinum diffusion temperature T ('C) and the interface charge t (Qss/q), and the amount of charge changes more negatively as the platinum diffusion temperature increases. It shows.

- On the other hand, the rate of diffusion of platinum into silicon varies depending on the temperature, and the rate of diffusion of platinum into silicon increases as the temperature rises. This shows in FIG. 2 that the higher the temperature, 8i0°, the greater the amount of platinum that reaches the silicon substrate interface. Also, Figure 3 is a characteristic diagram showing the relationship between the amount of charge and the withstand voltage (vCEO) (in the case of a transistor).As is clear from the figure, the larger the amount of negative (e) charge, the larger V tc's '6. It is clear that However, if platinum is diffused over the entire surface through the N-type semiconductor 5, for example, the lifetime of the portion that functions as a transistor will be shortened, the amplification factor hFB will be lowered, and the saturation voltage will be increased.

Therefore, in the present invention, by diffusing platinum from the surface of the guard ring portion 3 as shown in FIG. 1, platinum is diffused only into the pressure-resistant portion. As a result, the s51-5to interface electrons change from ■ ions to e ions, and the spread of the depletion layer at the surface increases as shown by 10 in FIG. 4, approaching the theoretical breakdown voltage. - On the other hand, since there is no platinum directly under the emitter that acts as a transistor, the lifetime is long and the amplification factor hFE and saturation characteristic Vσg (sat) do not deteriorate. By diffusing platinum only in the withstand voltage portion, the interfacial charge of 5t-sto is set to e, making it possible to manufacture a transistor 41i with a high withstand voltage and a high rate of increase. Incidentally, regarding the lateral range of Pt diffusion, it is necessary that almost no Pt be diffused into the emitter that functions as a transistor. That is, the maximum lateral diffusion distance is from the place where PT is introduced to the emitter at the shortest distance. Figure 5 is a characteristic diagram comparing selective diffusion and full-surface diffusion.As is clear from the hFE-Ic characteristics in the figure, the decrease in hFB in the large current region of the full-field diffusion product (A) is greater than that of the selection (0). . At I c = 5 A, the value was about 1/2 of hFFs = 17 for the selected product and hFE = 8 for the entire surface diffusion product. In the above explanation, the present invention was applied to a transistor, but if applied to a diode, it is possible to increase the withstand voltage and reduce the forward voltage (VF), and it can also be applied to a power MO8FRT and other thyristors. The applicability is obvious. Further, in the above embodiment, an example using a guard ring has been described, but the guard ring does not necessarily need to be provided, and it is sufficient if platinum is introduced into the breakdown voltage region where the depletion layer spreads.

As is clear from the above explanation, according to the present invention, it is possible to achieve a high withstand voltage even if the number of guard rings is smaller than before, and even if the depth of the guard ring is shallow, and the effect is greater for products with higher withstand voltages. This has great practical effects, such as being able to achieve high hFB and low saturation voltage, especially when applied to transistors, without the negative effects of platinum diffusion.

[Brief explanation of the drawing]

Figure 1 is a sectional view showing one embodiment of the present invention, Figures 2 and 3 are
FIG. 4 is a characteristic diagram, and FIG. 5 is a characteristic diagram of the present invention in comparison with a conventional example. In the figure, 1 is a silicon semiconductor base, 2 is a P-type semiconductor (base), 3 is a guard ring, and 4
is an N-type semiconductor (Emi, Ri), S is an N-type semiconductor (ohmic region), 6 is a channel strike, 7 is a platinum diffusion region, 8 is silicon g ($ r Ot ), 9 is an electrode metal, 10 is a depletion layer. Patent applicant Shindengen Industries Co., Ltd. Vcso (eLLloo), tA) QLSa/9f<xto”)

Claims (1)

[Claims] In a semiconductor device in which a P-N junction exposed on the surface of a silicon semiconductor substrate is coated with a silicon dioxide film, platinum is introduced into at least the interface between the substrate surface and the silicon dioxide film in the breakdown voltage region near the P-N junction. A high voltage semiconductor device characterized by: