JPS6355225B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a semiconductor device, in particular, to a semiconductor device by injecting electrons from a semiconductor layer provided on a channel layer and having a smaller electron affinity to a channel layer below a gate electrode. , relates to a field effect transistor whose operating speed is increased.

(b) Background of the technology In order to improve the operating speed of semiconductor devices and reduce power consumption, many transistors use compound semiconductors such as gallium arsenide (GaAs), which has a much higher carrier mobility than silicon (Si). Proposed. Field effect transistors (FETs) are transistors that use compound semiconductors.
(abbreviated as bipolar transistors) are currently the mainstream because their manufacturing process is simpler than that of bipolar transistors.
FET is widely used.

In a conventional semiconductor device such as Si or GaAs, carriers move within the semiconductor space where impurity ions are present. During this movement, carriers are scattered by lattice vibrations and impurity ions, but if the temperature is lowered to reduce the probability of scattering due to lattice vibrations, the probability of scattering by impurity ions increases, and the carrier mobility decreases. limited by.

In order to eliminate this impurity scattering effect, the region where the impurity is added and the region where the carriers move are spatially separated by a heterojunction interface to increase the mobility of the carriers, especially at low temperatures. Even higher speeds have been realized by field effect transistors (hereinafter simply referred to as heterojunction FETs).

(c) Prior Art and Problems An example of the conventional structure of the above-mentioned hetero-coupled FET is shown in FIG. 1a. A non-doped GaAs layer 2, an n-type aluminum gallium arsenide (AlGaAs) layer 3 having a smaller electron affinity and containing donor impurities, and an n-type GaAs layer 4 are formed on a semi-insulating GaAs substrate 1.
A gate electrode 7 is provided in contact with the n-type AlGaAs layer 3 by selectively removing the n-type GaAs layer 4 and, if necessary, a part of the n-type AlGaAs layer 3. A source electrode 8 and a drain electrode 9 are provided on the GaAs layer 4 . Non-doped GaAs from n-type AlGaAs layer 3 (referred to as electron supply layer)
A two-dimensional electron gas 6 generated near the heterojunction interface between both layers by electrons transferred to layer 2 (referred to as a channel layer) functions as a channel, and its electron concentration is changed by the voltage applied to the gate electrode 7. By controlling the source electrode 8 and the drain electrode 9
The impedance between the two is controlled.

In the conventional example, 10 is formed by patterning the source electrode 8 and the drain electrode 9 and then performing a heat treatment at a temperature of 450 [° C.] for about 2 minutes, so that the electrode metal is diffused into the semiconductor layer. The alloy region reaches the two-dimensional electron gas 6, and the source electrode 8 or drain electrode 9 and 2
It becomes a conductive path with low resistivity that connects to the dimensional electron gas 6.

FIG. 1b is an enlarged view of the main part when the conventional example is in the enhancement mode, and shows the drain electrode 9.
When a positive drain voltage is applied to the source electrode 8, electrons injected into the gate region G mainly flow into the two-dimensional electron gas layer 6 of the source region S.
For example, at a temperature of 77 [K] and an electronic surface concentration n=1×10 ¹² [cm ² ], the electron mobility μ=
A value of about 3×10 ⁴ [cm ² /V·S] has been obtained.

This electron mobility is sufficiently high compared to a GaAs shot key barrier FET with a normal structure, but it is used in electronic computers for scientific calculations to better demonstrate the effectiveness of a heterojunction FET. It is desired to further increase the electron mobility μ.

Some shot barrier type FEHs, which have a normal structure in which the carrier moves in a space into which impurities are introduced, have already been put into practical use, and the development of integrated circuit devices using them as elements is being promoted. Speeding up is also an important issue.

(d) Purpose of the Invention The purpose of the present invention is to improve the operation of an FET equipped with a gate electrode that makes occasional contact, and to promote faster operation of the FET.

(e) Structure of the Invention The object of the present invention is to provide a first semiconductor layer having a lower electron affinity than that of the first semiconductor layer;
a semiconductor substrate that forms a heterojunction with a semiconductor layer and is provided with a second semiconductor layer containing donor impurities, the first semiconductor layer being a channel layer, and in short contact with the semiconductor substrate. a gate electrode, and a source electrode and a drain electrode that are in ohmic contact with each other, and the alloy region with the source electrode metal in the base does not reach the heterojunction interface, and the alloy region with the drain electrode metal does not reach the heterojunction interface. It reaches the semiconductor layer of 1,
The heterojunction is applied from the boundary between the source region under the source electrode of the second semiconductor layer and the gate region under the gate electrode to the gate region under the gate electrode of the first semiconductor layer. This is achieved by a semiconductor device characterized in that electrons are directly injected with an initial velocity based on the difference in energy levels at the bottoms of the conductive bands of the first and second semiconductor layers.

(f) Embodiments of the Invention An embodiment of the semiconductor device according to the present invention includes a semiconductor device in which an alloy region with a source electrode metal within a semiconductor substrate does not reach a heterojunction interface.

FIG. 2a is an enlarged sectional view of a main part of a heterojunction FET that uses an enhancement mode two-dimensional electron gas as a channel, which corresponds to the above-mentioned embodiment;
2 is a non-doped GaAs channel layer, 13 is an n-type AlGaAs electron supply layer containing donor impurities, 14 is an n-type GaAs layer, 16 is a two-dimensional electron gas, 17 is a gate electrode, 18 is a source electrode, 19 is a drain electrode, 20 indicates the alloy region. In this embodiment, the alloy region 20 is formed only within the n-type GaAs layer 14 and does not reach the n-type AlGaAs electron supply layer 13. Therefore, the n-type AlGaAs electron supply layer 13
The energy band diagram near the heterojunction interface between the n-type AlGaAs electron supply layer 13 and the GaAs channel layer 12 shows a shape as shown in FIG. In the conduction band, △EC≒0.3 [eV]
There are differences in degree.

Similar to the conventional example, the channel of the semiconductor device of this example is formed by two-dimensional electron gas at the heterojunction interface between the GaAs channel layer 12 and the n-type AIGaAs electron supply layer 13. The energy of electrons injected into the gate region G is greater than in the conventional case.

That is, the electron supply layer 13 is doped with impurities at a high concentration and has a low resistivity, whereas the two-dimensional electron gas 16 has a restricted surface concentration. Therefore, in this embodiment, in which a low-resistance alloy region that reaches the two-dimensional electron gas layer 16 is not provided, the electrons that reach the channel in the region G under the gate from the source electrode 18 are the two-dimensional electrons in the source region S. Regardless of the gas, the path through which electrons are directly injected from the electron supply layer 13 into the region G becomes dominant. When viewed from the region G side, these directly injected electrons have higher energy than the electrons in the two-dimensional electron gas 16 by the energy difference ΔEC in the conduction band between the electron supply layer 13 and the channel layer 12, as shown in FIG. 2b. be. Therefore, the electrons in region G of the semiconductor device of the present invention have higher mobility than in the prior art.

As is clear from the above description, the improvement in electron mobility according to the present invention is achieved by the above-described structure on the source electrode 18 side, which is achieved by the region G of the channel layer 12 from the electron supply layer 13 under the source electrode 18 to the gate electrode 17. The electrons directly injected into the energy level difference △EC
The structure of the alloy region on the drain electrode 19 side does not affect the energy during electron injection. Therefore,
The alloy region on the drain electrode 19 side may not reach the bonding interface between the electron supply layer 13 and the channel layer 12 as shown in FIG. In order to connect the drain electrodes 9 and 19 with lower resistivity, it is advantageous to have a structure in which the alloy region of the drain electrode 9 in FIG. 1 reaches the channel layer 2.

Hereinafter, regarding the structure of the alloy region on the drain electrode side, in the first embodiment (shown in FIG. 3), the second embodiment
The second embodiment (shown in FIG. 4) shows the same structure as in FIG. 1 and will be described. Note that forming the drain electrode alloy region as shown in FIG. 1 in the first embodiment (FIG. 3) involves controlling the depth of the alloy region by the method described in the second embodiment. This is possible.

Examples of the present invention will be described in more detail below. FIG. 3 is a sectional view showing the first embodiment of the present invention. In the figure, 21 is a semi-insulating GaAs substrate, 22 is a non-doped GaAs layer, and 23 is a Si layer.
n-type AlGaAs layer doped to about ×10 ¹⁸ [cm ^-3 ],
24 is n doped with Si to about 2×10 ¹⁸ [cm ^-3 ]
26 is a two-dimensional electron gas, 27 is a gate electrode, 28 is a source electrode, and 29 is a drain electrode.

Conventionally, alloying with a gold-germanium/gold (AuGe/Au) electrode by heat treatment at a temperature of 450 [°C] for about 2 minutes has an electrode film thickness of 200°C.
[nm], the reaching depth is about 150 [nm], so in this example, n-type AlGaAs
The thickness of the layer 23 is about 30 [nm], but it is made of n-type GaAs.
The thickness of the layer 24 is about 250 [nm] and the alloy region 30
The structure of the present invention described above is realized with a depth of at least .

If we compare the characteristics of an equivalent element with a gate length LG = 0.25 [μm] between the first embodiment and the conventional example described above, we can see that, for example, the cutoff frequency at room temperature
T is approximately 80 [GHz] in the conventional example, whereas in the example, it is approximately 80 [GHz].
200 [GHz], and it has been demonstrated that the present invention is highly effective.

Next, as a second embodiment, FIG. 4 shows an example in which the present invention is applied to a shot barrier type FET in which impurities are introduced into the channel layer. In the figure,
41 is a semi-insulating GaAs substrate, 42 is, for example, 1 Si
Doped to about ×10 ¹⁷ [cm ^-3 ], thickness 170 [nm]
43 is the n-type GaAs layer 4.
n-type with the same concentration as 2 and a thickness of about 30 [nm], for example.
AlGaAs layer, 45 is an n ⁺ type GaAs layer, 47 is a gate electrode, 48 is a source electrode, 49 is a drain electrode,
50 is an alloy region.

In this embodiment, the thickness of the n ⁺ GaAs layer 45 is approximately
200 [nm], the AuGe/Au film thickness is approximately 200 [nm] for the source electrode, and approximately 300 [nm] for the drain electrode.
[nm], heat treatment is performed at a temperature of about 450 [°C] for about 2 minutes to form the alloy region 50 to a depth of about 150 [nm] for the source region and about 350 [nm] for the drain region. There is.

In this way, the depth of the alloy region 50 is selectively controlled, and the source region is an n-type channel layer.
No ohmic contact is formed in the GaAs layer 42, but an ohmic contact is formed in the drain region that reaches the channel layer. With this structure, electrons with high energy and initial velocity are injected into the channel layer, increasing the average velocity of the electrons and increasing the operating speed, as in the case where the channel layer is non-doped as described above.

In this embodiment, an ohmic contact reaching the channel layer is formed in the drain region to prevent an increase in resistance and to further enhance the effect of the present invention. A similar effect can be obtained when is non-doped.

(g) Effects of the Invention As explained above, according to the present invention, electron mobility is increased by injecting electrons with an initial velocity into the channel layer, and the compound developed for the purpose of high speed can be improved. The effect of further improving the operating speed of the semiconductor field effect transistor and increasing the transfer conductance gm in high frequency operation can be obtained.

[Brief explanation of the drawing]

1A and 1B are cross-sectional views showing a conventional example of a heterojunction FET, FIG. 2A is a sectional view showing an example of a structure according to the present invention, FIG. 1B is an energy band diagram thereof, and FIGS. The figure is a sectional view showing an embodiment of the present invention. In the figure, 1, 11, 21, and 41 are semi-insulating GaAs substrates, and 2, 12, and 22 are non-doped GaAs substrates.
GaAs layer, 42 is n-type GaAs layer, 3, 13, 23
and 43 are n-type AlGaAs layers, 4, 14 and 24 are n-type GaAs layers, 45 is a heavily doped n-type GaAs layer,
6, 16 and 26 are two-dimensional electron gases, 7, 17,
27 and 47 are gate electrodes, 8, 18, 28 and 48 are source electrodes, 9, 19, 29 and 49 are drain electrodes, and 10, 20, 30 and 50 are alloy regions.

Claims (1)

[Claims] 1 A first semiconductor layer and a second semiconductor layer having a lower electron affinity than the first semiconductor layer, forming a heterojunction with the first semiconductor layer, and containing donor impurities are provided. a semiconductor substrate, the first semiconductor layer as a channel layer, a gate electrode in spot contact with the semiconductor substrate, and a source electrode and a drain electrode in ohmic contact with the source electrode metal in the substrate; without allowing the alloy region to reach the heterojunction interface,
The alloy region with the drain electrode metal reaches the first semiconductor layer, and extends from the boundary between the source region under the source electrode of the second semiconductor layer and the gate region under the gate electrode. Directly injecting electrons having an initial velocity based on a difference in energy levels at the bottoms of conductive bands of the first and second semiconductor layers that are connected to the heterojunction into a gate region under the gate electrode of the first semiconductor layer. A semiconductor device characterized by: