JPH0236062B2 - HANDOTAISOCHI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an improvement in the structure of a semiconductor device, particularly to improve the reliability and characteristics of a compound semiconductor field effect transistor.

(b) Background of the technology Gallium arsenide (GaAs), which has a much higher carrier mobility than silicon (Si), is used to improve the operating speed of semiconductor devices and reduce power consumption.
A large number of transistors using compound semiconductors have been proposed. Field-effect transistors (hereinafter referred to as field-effect transistors) are transistors that use compound semiconductors.
FETs (abbreviated as FETs) are currently the mainstream because their manufacturing process is simpler than bipolar transistors, and Schottky barrier FETs are particularly popular.

In a semiconductor device such as Si or GaAs having a conventional structure, carriers move within a semiconductor space where impurity ions are present. During this movement, carriers are scattered by lattice vibrations and impurity ions, but if the temperature is lowered to reduce the probability of scattering due to lattice vibrations, the probability of scattering by impurity ions increases, and the carrier mobility decreases. limited by.

In order to eliminate this impurity scattering effect, the region where impurities are added and the region where carriers move are spatially separated by a heterojunction interface, increasing carrier mobility especially at low temperatures. Field-effect transistors (hereinafter abbreviated as heterojunction FETs) have been developed, and have achieved even higher speeds.

(c) Prior Art and Problems An example of the conventional structure of the heterojunction FET is shown in FIG. 1a. A non-doped i-type GaAs layer 2 and a non-doped i-type aluminum gallium arsenide (AlGaAs) layer 3 are provided on a semi-insulating GaAs substrate 1 . In this case, layer 2 and layer 3 are here referred to as first semiconductor layers, and layer 2 is i-type like layer 3.
It may also be AlGaAs.

A non-doped i-type GaAs layer 4 as a second semiconductor layer is provided on this first semiconductor layer, and a third
An n-type AlGaAs layer 5 is provided as a semiconductor layer, and an n-type GaAs layer 6 is provided thereon.

AlGaAs has a lower electron affinity than GaAs, and from the n-type AlGaAs layer 5 (referred to as electron supply layer) as the third semiconductor layer to the i-type GaAs as the second semiconductor layer.
A two-dimensional electron gas 4A generated near the heterojunction interface of the i-type GaAs layer 4 by electrons transferred to the layer (referred to as a channel layer) functions as a channel. The gate electrode 7 that controls the surface concentration of the two-dimensional electron gas 4A has a recessed structure in which the n-type GaAs layer 6 is selectively removed.
It is located adjacent to the Note that 8 is a source electrode and 9 is a drain electrode, and the n-type GaAs layer 6 is provided for good connection of these electrodes, and these electrodes are in low resistance ohmic contact with the semiconductor substrate by the alloy region 10. I am getting .

In the conventional example, the thickness of each semiconductor layer is as follows:
The n-type GaAs layer 6 is 50 [nm] thick, and the n-type AlGaAs layer 5 is
30 [nm], i-type GaAs layer 4 is 300 [nm], i-type
AlGaAs layer 3 is 100 [nm], i-type GaAs layer 2 is 200 nm
[nm], and the depth of the two-dimensional electron gas 4A is about 1 [nm] from the heterojunction interface. In this case, the second semiconductor layer is the i-type GaAs layer 4 and the first semiconductor layer is made of the i-type AlGaAs layer 3 and the i-type GaAs layer 2.
The semiconductor layer is a buffer layer for improving crystallinity, and has the role of making the upper surface of the second semiconductor layer have an intrinsic crystal structure. That is, the first and second semiconductor layers have a thickness necessary to perform a function necessary for improving crystallinity when a compound semiconductor is epitaxially grown on a substrate.

A cross-sectional view in the gate width direction of a conventional example in which isolation between elements is performed by mesa-shaped etching in an integrated circuit using a heterojunction FET element is shown in Fig. 1b, and the correspondence with Fig. 1a is shown in Fig. 1b. Indicated by the same reference numerals. The wiring connection region of the gate electrode 7 is provided outside the mesa-shaped operating region, and there is a step difference between the wiring connection region and the gate electrode portion.

This wiring connection area undergoes two etching processes: mesa etching and recess etching.
In either process, AlGaAs also has the function of a stopper when GaAs is selectively removed. Therefore, in the case of mesa etching, the i-type AlGaAs layer as the first semiconductor layer is used as a stopper for the subsequent recess etching. In some cases, n-type AlGaAs as the third semiconductor layer
The layer acts as a stopper. In this way, the gate wiring connection region becomes the upper surface of the i-type AlGaAs layer 3, and the step of the mesa structure is
It is approximately 330 [nm].

Furthermore, the thickness of the metal layer forming the gate electrode 7 is conventionally most commonly about 300 [nm], which is less than the above-mentioned step, and as a result, the metal layer becomes thinner at this step, as shown in FIG. 1b. This will lead to an increase in the resistance value, and there is also a risk of wire breakage at this part.

(d) Object of the Invention An object of the present invention is to address the above-mentioned problems and provide a structure of a semiconductor device that suppresses and prevents an increase in the resistance value and disconnection of the gate electrode.

(e) Structure of the Invention The object is to provide a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked on a semiconductor substrate according to the present invention, and the first semiconductor layer has a stopper function during etching for forming a mesa. At least the upper layer of the layer is made of a non-doped layer of the first compound semiconductor, and the second semiconductor layer is made of a non-doped layer of the first compound semiconductor, which has a high etching rate and a high electron affinity with the same etching solution as the first compound semiconductor. The third semiconductor layer is made of a second compound semiconductor, and the third semiconductor layer is made of a doped layer of the first compound semiconductor that acts as an electron supply layer.The first semiconductor layer and the second semiconductor layer are necessary for improving the crystallinity of the surface of the second semiconductor layer. The second semiconductor layer has a thickness that can function as a buffer layer, and the second semiconductor layer is located near the heterojunction interface with the third semiconductor layer and has the minimum thickness necessary to generate a two-dimensional electron gas of approximately 1 nm that functions as a channel layer. The thickness is approximately selected to be the thickness necessary for the first semiconductor layer to function as a buffer layer, the second semiconductor layer and the third semiconductor layer on the first semiconductor layer have a mesa structure, and the gate electrode is formed on the third semiconductor layer. The metal layer forming the gate electrode is provided in contact with the third and second metal layers.
The metal layer has a structure such that it extends along the mesa-forming surface of the semiconductor layer to the exposed surface of the first semiconductor layer, and the thickness of the metal layer is selected to be larger than the thickness of the stack of the second and third semiconductor layers. This is achieved by a semiconductor device characterized by:

That is, in the past, the second semiconductor layer functioned not only as a channel layer but also as a buffer layer together with the first semiconductor layer, but in the present invention, the second semiconductor layer functions as a channel layer made of about 1 nm of two-dimensional electron gas. The minimum thickness required for the configuration, while the first
The thickness of the semiconductor layer is set so that it can fulfill the function necessary for improving crystallinity, so that the thickness of the second and third semiconductor layers, which are the steps of the mesa, can be made small, and the thickness of the metal layer of the gate electrode can be made small. The semiconductor device is configured such that the step is larger than the step.

(f) Embodiment of the invention In an embodiment of the invention, the first compound semiconductor is AlGaAs, and the second compound semiconductor is AlGaAs.
The first example is GaAs.

Hereinafter, the present invention will be specifically described by way of examples with reference to the drawings.

FIG. 2a is a sectional view showing an embodiment of the present invention. In the figure, 11 is a semi-insulating GaAs substrate;
2 is a non-doped i-type GaAs layer, 13 is a non-doped i-type AlGaAs layer, and these two layers are combined to form the first layer.
A semiconductor layer, at least the upper part of this layer may be a non-doped i-type AlGaAs layer, and the layer 2 may be a non-doped i-type AlGaAs layer.
may have the same configuration as layer 3, and 14 is the second layer.
Non-doped i-type GaAs layer as a semiconductor layer, 1
5 is an n-type AlSaAs layer as the third semiconductor layer, 16
is an n-type GaAs layer, and the structure of the semiconductor layer is the same as that of the conventional example.

Furthermore, the thickness of the n-type GaAs layer 16 is, for example, 50 [n
m], the thickness of the n-type AlGaAs layer 15 is, for example, 30 [n
m] may be the same as that of the conventional example. In addition, type i
GaAs layer 14, i-type AlGaAs layer 13 and i-type GaAs
The total thickness of the layer 12 is also 600 [n] as in the conventional example.
m].

However, as mentioned earlier, the two-dimensional electron gas 14A is generated near the upper heterojunction interface of the i-type GaAs layer 14, but the depth thereof is, for example, about 1 [nm], so the second semiconductor layer is used as a channel layer. Therefore, if the lower heterojunction semiconductor layer is non-doped i-type, the i-type GaAs layer 1
4, and may be made as thin as, for example, about 10 nm. For example, even if the thickness is reduced from 300 nm in the conventional example to about 10 [nm], the two-dimensional electron gas 14A is not affected, and the characteristics of the heterojunction FET are not impaired. This requires that the first semiconductor layer (in this example, the sum of layers 12 and 13) have a thickness necessary for improving crystallinity.

Based on this fact, in this example, the thickness of the i-type GaAs layer 14 as the second semiconductor layer is set to 50 mm.
[nm], and the thickness of the i-type AlGaAs layer 13 and the i-type GaAs layer 12 constituting the first semiconductor layer is 250 [nm].
m] and about 300 [nm]. Therefore n-type
i as the first semiconductor layer from the top surface of the GaAs layer 16
The depth to the top surface of type AlGaAs layer 13 is 130 [nm]
The depth from the upper surface of the n-type AlGaAs layer 15 of the third semiconductor layer is approximately 80 [nm].

With the thickness of the semiconductor layer as described above, selective etching using the i-type AlGaAs layer 13 of the first semiconductor layer as a stop layer can be effectively applied to mesa etching for element isolation. After this mesa etching, a recess can be formed by selective dry etching using the n-type AlGaAs layer 15 as a third semiconductor layer as a stop layer.

As a result, the difference in level between the electrode portion of the gate electrode 17 and the wiring connection region is 80 [nm] in this embodiment.
As shown in Figure 2b, even if the thickness of the gate electrode metal layer is set to about 300 [nm], which is the same as before, the risk of wire breakage is eliminated and the resistance value is kept low. .

In the embodiments described above, the step difference between the gate electrode metal layer forming surfaces is extremely small;
This step, that is, the i-type AlGaAs layer 1 of the first semiconductor
From the top surface of 3, the n-type AlGaAs layer 15 of the third semiconductor layer
The distance to the top surface of the first semiconductor layer is i-type
If the thickness is smaller than the thickness of the gate electrode metal layer on the surface of the AlGaAs layer 13, the object of the present invention has been achieved.

Furthermore, the structure of the present invention is not limited to GaAs/AlGaAs compounds, but can be extended to other compound semiconductors.

(g) Effects of the Invention As explained above, according to the present invention, the increase in resistance value and the risk of disconnection due to the step difference in the gate electrode metal layer, which have been problems in the prior art in compound semiconductor devices as the object of the present invention, can be avoided. suppressed and prevented to improve its performance and reliability.

[Brief explanation of drawings]

1A and 1B show an example of a conventional semiconductor device, and FIGS. 2A and 2B show an embodiment of the present invention. In the figure, 11 is a semi-insulating GaAs substrate, 12
and 14 is an i-type GaAs layer, 13 is an i-type AlGaAs layer,
15 is an n-type AlGaAs layer, 16 is an n-type GaAs layer, 1
7 is a gate electrode, 18 is a source electrode, 19 is a drain electrode, and 20 is an alloy region.

Claims (1)

[Claims] 1 A first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are laminated on a semiconductor substrate, and at least the upper layer of the first semiconductor layer has a stopper function during etching for forming a mesa. The second semiconductor layer is made of a non-doped layer of a compound semiconductor, and the second semiconductor layer is made of a second compound semiconductor that has a higher etching rate and electron affinity in the same etching solution as the first compound semiconductor. The layer is made of a first compound semiconductor and is a doped layer that acts as an electron supply layer, and the first semiconductor layer and the second semiconductor layer have a thickness that can function as a buffer layer necessary for improving the crystallinity of the surface of the second semiconductor layer. The second semiconductor layer is located near the heterojunction interface with the third semiconductor layer and has the minimum thickness necessary to generate a two-dimensional electron gas of about 1 nm, which functions as a channel layer, and the first semiconductor layer is a buffer layer. The second semiconductor layer and the third semiconductor layer on the first semiconductor layer have a mesa structure, and the gate electrode is provided in contact with the third semiconductor layer to form the gate electrode. The metal layer has a structure in which the metal layer extends along the mesa forming surfaces of the third and second semiconductor layers to the exposed surface of the first semiconductor layer, and the thickness of the metal layer is equal to the thickness of the second and third semiconductor layers. A semiconductor device characterized in that the thickness of the semiconductor device is selected to be greater than the thickness of the laminated layers.