JPS6352490B2 - - Google Patents
Info
- Publication number
- JPS6352490B2 JPS6352490B2 JP53094784A JP9478478A JPS6352490B2 JP S6352490 B2 JPS6352490 B2 JP S6352490B2 JP 53094784 A JP53094784 A JP 53094784A JP 9478478 A JP9478478 A JP 9478478A JP S6352490 B2 JPS6352490 B2 JP S6352490B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- nand gate
- mos
- gate circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 16
- 230000000903 blocking effect Effects 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims 1
- 230000000630 rising effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
＜産業上の利用分野＞
この発明は半導体ロジツク回路に使用するパル
ス発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a pulse generation circuit used in a semiconductor logic circuit.
＜従来の技術＞
記憶素子等を含むロジツク回路においては、記
憶素子を初期リセツト状態にするため電源投入と
同時にリセツトパルスを発生するようにしてい
る。<Prior Art> In a logic circuit including a memory element, etc., a reset pulse is generated at the same time as power is turned on to bring the memory element into an initial reset state.
この目的のため一般にはコンデンサと抵抗素子
からなるCR積分回路を主たる構成要素としたパ
ルス発生回路が使用されている。 For this purpose, a pulse generating circuit whose main component is a CR integrating circuit consisting of a capacitor and a resistive element is generally used.
しかし、上記のようなパルス発生回路の場合、
通常の電源入りの時は所望のリセツトパルスが得
られるが、急速に電源を入り、切りした場合、例
えば電源が瞬断したような場合コンデンサの放電
がこれに追従できないため確実にリセツトパルス
を発生させることが不可能となりロジツク回路が
誤動作することがある。 However, in the case of a pulse generation circuit like the one above,
When the power is turned on normally, the desired reset pulse can be obtained, but if the power is turned on and turned off rapidly, for example when the power is momentarily cut off, the capacitor discharge cannot follow this and a reset pulse must be generated reliably. It may become impossible to do so, and the logic circuit may malfunction.
これを解決するためには電源断時すなわち電源
電圧低下時にもリセツトパルスを発生するように
すればよく、このための一実施例として特開昭51
−82556のようなパルス発生回路が提案されてい
る。 In order to solve this problem, it is sufficient to generate a reset pulse even when the power supply is cut off, that is, when the power supply voltage drops.
Pulse generation circuits such as the -82556 have been proposed.
ところで該実施例では、電源入りの時にはトラ
ンジスタのベース電位を大きい時定数で上昇させ
るとともに、エミツタ電位を小さい時定数で上昇
させ、電源切りの時には上記ベース電位を小さい
時定数で下降させるとともに、上記エミツタ電位
を大きい時定数で下降させることにより、電源入
りおよび切りのときに上記トランジスタのコレク
タより上記各時定数によつて定まる時間巾を有す
るパルスを得るように回路が構成されており、具
体的にはトランジスタQ1のエミツタとアース間
にコンデンサC2を接続し、電源＋Ｂとトランジ
スタQ1のエミツタ間にダイオードをその導通方
向をエミツタ側に向けて接続してある。またトラ
ンジスタQ1のコレクタは抵抗R1を通してアース
に接続され、コレクタと抵抗R1の接続点からパ
ルス出力が取り出せるようにしてある。さらにト
ランジスタQ1のベースは抵抗R8とR2の直列接続
回路を通して電源＋Ｂに接続され、そして抵抗
R3とR2の接続点を、一方はコンデンサC1を通し
てアースに接続し、他方はダイオードD1をその
導通方向を電源＋Ｂ側に向けて電源＋Ｂに接続し
ている。 By the way, in this embodiment, when the power is turned on, the base potential of the transistor is raised with a large time constant, and the emitter potential is raised with a small time constant, and when the power is turned off, the base potential is lowered with a small time constant, and the By lowering the emitter potential with a large time constant, the circuit is configured to obtain a pulse having a time width determined by each of the above time constants from the collector of the transistor when the power is turned on and off. A capacitor C2 is connected between the emitter of the transistor Q1 and the ground, and a diode is connected between the power supply +B and the emitter of the transistor Q1 with its conducting direction facing the emitter side. The collector of transistor Q 1 is connected to ground through resistor R 1 so that a pulse output can be taken out from the connection point between the collector and resistor R 1 . Furthermore, the base of transistor Q 1 is connected to the power supply +B through a series connection circuit of resistors R 8 and R 2 , and
One of the connecting points of R 3 and R 2 is connected to the ground through a capacitor C 1 , and the other is connected to the power supply +B with a diode D 1 with its conduction direction facing the power supply +B side.
＜発明が解決しようとする問題点＞
上記の構成によれば、電源の入りおよび切りの
いずれの瞬間においてもパルス出力を得ることが
でき、これを半導体ロジツク回路のリセツトパル
スに利用することができるが、次のような問題点
を有する。すなわち
トランジスタQ1のエミツタ電位とベース電
位の電位差が、ベース・エミツタ間電圧VBEを
超過するとパルスを発生するため比較的小さい
電源電圧変動でもパルスを発生し、リセツトパ
ルスとしての使用には不都合である。<Problems to be Solved by the Invention> According to the above configuration, a pulse output can be obtained at any instant when the power is turned on or off, and this can be used as a reset pulse for a semiconductor logic circuit. However, it has the following problems. In other words, if the potential difference between the emitter potential and the base potential of transistor Q1 exceeds the base-emitter voltage V BE , a pulse is generated, so even a relatively small fluctuation in the power supply voltage generates a pulse, which is inconvenient for use as a reset pulse. be.
トランジスタQ1のベース側コンデンサC1の
充電時定数およびエミツタ側コンデンサC2の
放電時定数が、回路の制約によつて余り大きく
できないため、電源入り時の電圧の立上り速
度、および電源切り時の電圧の立下り速度がき
わめて緩慢である場合には、パルスが得られな
いことがある。 Because the charging time constant of the base capacitor C 1 and the discharging time constant of the emitter capacitor C 2 of the transistor Q 1 cannot be made too large due to circuit constraints, the voltage rise speed when the power is turned on and the voltage rise speed when the power is turned off are If the rate of fall of the voltage is extremely slow, pulses may not be obtained.
パルス発生回路の動作点が自由に設定できな
い。 The operating point of the pulse generation circuit cannot be set freely.
ということがある。That's what happens.
本発明の目的は、電源入り、切り時の電圧の立
上りおよび立下がりの速度が速い場合でも、また
逆に極めて緩慢な場合でも確実にリセツトパルス
を発生することができ、かつ、電源電圧変動によ
る不必要なリセツトパルスが発生せず、しかも回
路の動作点が適宜設定可能なパルス発生回路を提
供することにある。 An object of the present invention is to be able to reliably generate a reset pulse even when the voltage rises and falls at high speeds when the power is turned on and off, or even when the voltage rises and falls at a very slow speed, and that It is an object of the present invention to provide a pulse generating circuit that does not generate unnecessary reset pulses and can set the operating point of the circuit appropriately.
＜問題点を解決するための手段＞
この発明のパルス発生回路はＣ−MOSナンド
ゲート回路の入力および電源の超低消費電力性能
を利用して、電源入りのときは、Ｃ−MOSナン
ドゲート回路の電源端子電圧の立上り速度を、Ｃ
−MOSナンドゲート回路の一方の入力端子の電
圧の立上り速度より速くし、また電源切りのとき
はＣ−MOSナンドゲート回路の電源端子電圧の
立下り速度を、Ｃ−MOSナンドゲート回路の一
方の入力端子の電圧の立下り速度より遅くするこ
とで、Ｃ−MOSナンドゲート回路の一方の入力
端子の電位が、Ｃ−MOSナンドゲート回路のス
レツシホールド電圧より低いときにＣ−MOSナ
ンドゲート回路の出力端子よりパルスを得るよう
にしたものである。<Means for Solving the Problems> The pulse generating circuit of the present invention utilizes the ultra-low power consumption performance of the input and power supply of the C-MOS NAND gate circuit, and when the power is turned on, the power supply of the C-MOS NAND gate circuit is The rising speed of the terminal voltage is C
-The rising speed of the voltage at one input terminal of the C-MOS NAND gate circuit is set faster than the rising speed of the voltage at one input terminal of the C-MOS NAND gate circuit, and when the power is turned off, the falling speed of the voltage at the power supply terminal of the C-MOS NAND gate circuit is By making it slower than the falling speed of the voltage, a pulse is generated from the output terminal of the C-MOS NAND gate circuit when the potential of one input terminal of the C-MOS NAND gate circuit is lower than the threshold voltage of the C-MOS NAND gate circuit. It was designed to be obtained.
＜作用＞
前記構成のパルス発生回路であれば、Ｃ−
MOSナンドゲート回路を使用することにより電
源の入り、切りに伴なう電源電圧の変化が急激な
ものであつても、また極めて緩慢であつても確実
にリセツトパルスを発生することができる。また
Ｃ−MOSナンドゲート回路のスレツシホールド
電圧以内の電源電圧変動によるリセツトパルスの
誤出力はなく、したがつて電圧変動による不必要
なリセツトパルスの出力がない。<Function> If the pulse generating circuit has the above configuration, C-
By using a MOS NAND gate circuit, a reset pulse can be reliably generated even when the power supply voltage changes rapidly or extremely slowly when the power is turned on and off. Further, there is no erroneous output of reset pulses due to power supply voltage fluctuations within the threshold voltage of the C-MOS NAND gate circuit, and therefore no unnecessary reset pulses are output due to voltage fluctuations.
＜実施例＞
本発明の一実施例を第１図、および第２図によ
り詳細に説明する。<Example> An example of the present invention will be described in detail with reference to FIGS. 1 and 2.
第１図に示す接続図において、１，２は制御電
源入力端子、３は電源スイツチ、４はＣ−MOS
ロジツク回路用定電圧電源、５，８はダイオー
ド、７，９はコンデンサ、６は抵抗、１０はＣ−
MOSナンドゲート回路で、１０１，１０２はそ
の入力端子、１２，１３はＣ−MOSロジツク回
路に接続される電源４の出力端子、１１はリセツ
トパルス出力端子である。 In the connection diagram shown in Figure 1, 1 and 2 are control power input terminals, 3 is a power switch, and 4 is a C-MOS
Constant voltage power supply for logic circuit, 5, 8 are diodes, 7, 9 are capacitors, 6 is resistor, 10 is C-
In the MOS NAND gate circuit, 101 and 102 are its input terminals, 12 and 13 are output terminals of a power supply 4 connected to the C-MOS logic circuit, and 11 is a reset pulse output terminal.
次に動作を第２図のタイムチヤートを参照して
説明する。今、端子１，２間に制御電源を与えス
イツチ３を閉じると、Ｃ−MOSナンドゲート１
０の電源端子１０３，１０４の電圧e4はダイオー
ド８を介し電源４の電圧e2に追従して立上り、該
ナンドゲート１０の一方の入力端子１０２の電圧
e3はe2の立上り時間（時定数）に、抵抗６及びコ
ンデンサ７とで決定される時定数が加わつて、e2
よりゆるやかに立上る。次にスイツチ３を開く
と、電圧e3はダイオード５を介しe2に追従して立
下り、コンデンサ９の端子電圧e4はコンデンサ９
の電荷がダイオード８の存在により抵抗値が極め
て高いＣ−MOSナンドゲート回路１０の電源端
子１０３，１０４を介して放電されるのみため、
極めてゆるやかに立下る。次にt1時間経過後即ち
０＜e2＜eLのとき再びスイツチ３を閉じると、e3
はその時の電圧値（＝e2）から抵抗６及びコンデ
ンサ７で決定される時定数が加わつて、e2よりゆ
るやかに立上り、電圧e4はe2より大きい間ゆるや
かに放電を設け、e4＜e2になるとe2に追従して立
上る。ここで、一点鎖線で示す曲線eTHはＣ−
MOSナンドゲート回路１０のスレツシホールド
電圧とよばれるもので、ナンドゲート回路１０の
電源電圧e4に追従し、その略々1/2の値である。
又、波状で示すeLは端子１２，１３に接続される
Ｃ−MOSロジツク回路の動作が不安定な電圧範
囲（レベル）である。 Next, the operation will be explained with reference to the time chart shown in FIG. Now, when control power is applied between terminals 1 and 2 and switch 3 is closed, C-MOS NAND gate 1
The voltage e 4 at the power supply terminals 103 and 104 of 0 rises following the voltage e 2 of the power supply 4 via the diode 8, and the voltage at the input terminal 102 of one of the NAND gates 10 rises.
e 3 is the rise time (time constant) of e 2 plus the time constant determined by the resistor 6 and capacitor 7, and e 2
Rise more slowly. Next, when switch 3 is opened, voltage e 3 follows e 2 through diode 5 and falls, and terminal voltage e 4 of capacitor 9 changes to capacitor 9.
Since the electric charge is only discharged through the power supply terminals 103 and 104 of the C-MOS NAND gate circuit 10, which has an extremely high resistance value due to the presence of the diode 8,
It falls extremely slowly. Next, when the switch 3 is closed again after t 1 hour has elapsed, that is, 0 < e 2 < eL, e 3
A time constant determined by the resistor 6 and capacitor 7 is added to the voltage value at that time (=e 2 ), and the voltage e 4 rises more slowly than e 2 , and the voltage e 4 is discharged slowly while it is greater than e 2 , and e 4 When < e 2 , it follows e 2 and rises. Here, the curve e TH shown by the dashed line is C-
This is called the threshold voltage of the MOS NAND gate circuit 10, and follows the power supply voltage e4 of the NAND gate circuit 10, and has a value of approximately 1/2 thereof.
Further, e L shown in a waveform is a voltage range (level) in which the operation of the C-MOS logic circuit connected to the terminals 12 and 13 is unstable.
而して、第１回目のスイツチ３を閉じた後eTH
＞e3の間、つまりナンドゲート回路１０の一方の
入力端子１０２の電圧e3がスレツシホールド電圧
eTHより低いので、ナンドゲート回路１０は反転
してその出力端子１１よりリセツトパルスを発す
る。このパルスにより端子１２，１３に接続され
る図示しないＣ−MOSロジツク回路は電源投入
と同時に一斉に初期リセツトされる。次に電源が
t1時間瞬断した場合もeTH＞e3の間同様にリセツト
パルスを発し、更に電源がt1より長いt2時間断状
態となつてもeTH＞e3の間同様にリセツトパルス
を発する。各斜線で示す部分が端子１１より送出
されるリセツトパルスの波形である。 Then, after closing switch 3 for the first time, e TH
> e 3 , that is, the voltage e 3 at one input terminal 102 of the NAND gate circuit 10 is the threshold voltage.
Since e is lower than TH , the NAND gate circuit 10 is inverted and outputs a reset pulse from its output terminal 11. By this pulse, the C-MOS logic circuits (not shown) connected to the terminals 12 and 13 are initialized all at once when the power is turned on. Then the power
Even if there is a momentary power outage for t 1 hour, a reset pulse will be issued in the same way while e TH > e 3 , and even if the power supply is cut off for t 2 hours longer than t 1 , a reset pulse will be issued in the same way while e TH > e 3 . emanate. The shaded portions are the waveforms of the reset pulses sent from the terminals 11.
なお、第１図に点線で示す抵抗１４，１５を接
続し、電圧e2を分圧してナンドゲート回路１０の
他方の入力端子１０１に加えるようにすればスレ
ツシホールド電圧を見かけ上、高くすることがで
き電源４の電圧e2が正規の電圧値の約50〜100％
の範囲で且つ任意の値以下に低下したときリセツ
トパルスを発生させることができる。もし、抵抗
１４，１５を接続しないときは、ナンドゲート１
０の他方の入力端子１０１を一方の入力端子１０
２又は電源の出力端子１２に接続しておけばよ
い。 Note that by connecting the resistors 14 and 15 shown by dotted lines in FIG. 1 and dividing the voltage e2 and applying it to the other input terminal 101 of the NAND gate circuit 10, the threshold voltage can be made higher apparently. The voltage of power supply 4 can be about 50-100% of the normal voltage value
A reset pulse can be generated when the voltage falls within a range of 0 and below an arbitrary value. If resistors 14 and 15 are not connected, NAND gate 1
0's other input terminal 101 to one input terminal 10
2 or the output terminal 12 of the power supply.
またＣ−MOSナンドゲート回路は、極めて低
い入力エネルギーおよび電源エネルギーで動作す
るためその入力抵抗および電源の抵抗は極めて高
く実質無限大であり、したがつて外部CR積分回
路の定数は該ナンドゲート回路の影響を考慮する
ことなく自由に決定できる利点がある。 In addition, since the C-MOS NAND gate circuit operates with extremely low input energy and power supply energy, its input resistance and power supply resistance are extremely high and virtually infinite. Therefore, the constant of the external CR integration circuit is influenced by the NAND gate circuit. The advantage is that decisions can be made freely without considering the
＜効果＞
本発明のパルス発生回路によれば前述の通りＣ
−MOSナンドゲート回路の入力および電源の超
低消費電力性能により、該ナンドゲート回路の入
力端子および電源端子に接続するCR積分回路は
実質的に該ナンドゲート回路の影響を受けること
がなく、つねにその時定数を電源電圧の立上り時
定数および立下り時定数より大きく選定すること
ができるため、電源の入り、切りに伴なう電源電
圧の変化が急激であつても、また、逆に極めて緩
慢であつても確実にリセツトパルスを発し、Ｃ−
MOSロジツク回路を確実にリセツトすることが
でき、かつ、該ナンドゲート回路の一方の入力端
子の電圧が該ナンドゲート回路のスレツシホール
ド電圧以下になつたときのみリセツトパルスを発
生するため、トランジスタを用いた公知のものの
ように電源電圧の変動によつて不必要にパルスを
発することがなく、さらに該ナンドゲート回路の
他方の入力端子の電圧を抵抗分圧回路により適当
な値に設定することでパルス発生回路の動作点を
自由に設定し、リセツトパルスのパルス幅を調整
することができるといつた効果を奏する。<Effects> According to the pulse generation circuit of the present invention, as described above, C
- Due to the ultra-low power consumption performance of the input and power supply of the MOS NAND gate circuit, the CR integration circuit connected to the input terminal and power supply terminal of the NAND gate circuit is virtually unaffected by the NAND gate circuit, and always maintains its time constant. The rise and fall time constants of the power supply voltage can be selected to be larger than the rise and fall time constants of the power supply voltage, so even if the power supply voltage changes rapidly as the power is turned on and off, or conversely, even if it is extremely slow. Make sure to issue a reset pulse and
In order to be able to reliably reset the MOS logic circuit and to generate a reset pulse only when the voltage at one input terminal of the NAND gate circuit falls below the threshold voltage of the NAND gate circuit, a transistor is used. The pulse generating circuit does not emit pulses unnecessarily due to fluctuations in the power supply voltage unlike the known ones, and furthermore, the voltage of the other input terminal of the NAND gate circuit is set to an appropriate value using a resistor voltage divider circuit. The operating point of the reset pulse can be freely set and the pulse width of the reset pulse can be adjusted.
第１図は発明を実施したパルス発生回路の接続
図、第２図はその動作説明用のタイムチヤートで
ある。
４……定電圧電源、５……放電用ダイオード、
６……抵抗、７，９……コンデンサ、８……放電
阻止用ダイオード、１０……Ｃ−MOSナンドゲ
ート回路、１１……リセツトパルス出力端子。
FIG. 1 is a connection diagram of a pulse generating circuit embodying the invention, and FIG. 2 is a time chart for explaining its operation. 4... constant voltage power supply, 5... discharge diode,
6...Resistor, 7,9...Capacitor, 8...Discharge blocking diode, 10...C-MOS NAND gate circuit, 11...Reset pulse output terminal.
Claims (1)
源投入後徐々に電圧が安定し且つ制御電源断後
徐々に電圧が低下するような定電圧電源４を有し
前記定電圧電源４の出力端子１２，１３間にＣ−
MOSロジツク回路等を接続したものにおいて、
前記出力端子１２，１３間に抵抗６とコンデンサ
７の直列回路及び放電阻止用ダイオード８とコン
デンサ９の直列回路をそれぞれ接続しＣ−MOS
ナンドゲート回路１０の一方の入力端子１０２を
上記抵抗６とコンデンサ７の間に接続すると共に
放電用ダイオード５を介し出力端子１２に接続
し、上記Ｃ−MOSナンドゲート回路１０の他方
の入力端子１０１を、上記一方の入力端子１０２
または上記出力端子１２のいずれかに接続し、上
記Ｃ−MOSナンドゲート回路１０の電源端子１
０３を上記放電阻止用ダイオード８とコンデンサ
９の間に接続し電源端子１０４を出力端子１３に
接続してなり、Ｃ−MOSナンドゲート回路１０
の一方の入力端子１０２の電圧が前記Ｃ−MOS
ナンドゲート回路のスレツシホールド電圧より低
いとき前記Ｃ−MOSナンドゲート回路１０の出
力端子１１よりパルスを送出するようにしたパル
ス発生回路。 ２ 出力端子１２，１３間の電圧を抵抗１４，１
５により分圧し、この分圧した電圧をＣ−MOS
ナンドゲート回路１０の他方の入力端子１０１に
加えるようにした特許請求の範囲第１項記載のパ
ルス発生回路。[Scope of Claims] 1. A constant voltage power source 4 which is connected to a control power source and whose voltage is gradually stabilized after the control power source is turned on and whose voltage gradually decreases after the control power source is turned off. C- between output terminals 12 and 13 of power supply 4
In those connected to MOS logic circuits, etc.
A series circuit of a resistor 6 and a capacitor 7 and a series circuit of a discharge blocking diode 8 and a capacitor 9 are connected between the output terminals 12 and 13, respectively.
One input terminal 102 of the NAND gate circuit 10 is connected between the resistor 6 and the capacitor 7 and connected to the output terminal 12 via the discharge diode 5, and the other input terminal 101 of the C-MOS NAND gate circuit 10 is connected to the output terminal 12 through the discharge diode 5. One of the above input terminals 102
Or connect it to any of the output terminals 12, and connect it to the power supply terminal 1 of the C-MOS NAND gate circuit 10.
03 is connected between the discharge blocking diode 8 and the capacitor 9, and the power supply terminal 104 is connected to the output terminal 13, thereby forming the C-MOS NAND gate circuit 10.
The voltage at one input terminal 102 of the C-MOS
A pulse generating circuit configured to send out a pulse from the output terminal 11 of the C-MOS NAND gate circuit 10 when the voltage is lower than the threshold voltage of the NAND gate circuit. 2 The voltage between output terminals 12 and 13 is connected to resistors 14 and 1.
5, and this divided voltage is applied to the C-MOS
The pulse generating circuit according to claim 1, wherein the pulse generating circuit is applied to the other input terminal 101 of the NAND gate circuit 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9478478A JPS5521656A (en) | 1978-08-02 | 1978-08-02 | Pulse generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9478478A JPS5521656A (en) | 1978-08-02 | 1978-08-02 | Pulse generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5521656A JPS5521656A (en) | 1980-02-15 |
| JPS6352490B2 true JPS6352490B2 (en) | 1988-10-19 |
Family
ID=14119696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9478478A Granted JPS5521656A (en) | 1978-08-02 | 1978-08-02 | Pulse generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5521656A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0641589U (en) * | 1992-11-16 | 1994-06-03 | 起夫 西田 | Body wash |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59147328U (en) * | 1983-03-19 | 1984-10-02 | 善工舎時計株式会社 | delay circuit |
-
1978
- 1978-08-02 JP JP9478478A patent/JPS5521656A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0641589U (en) * | 1992-11-16 | 1994-06-03 | 起夫 西田 | Body wash |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5521656A (en) | 1980-02-15 |
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