JPS59147328U - delay circuit - Google Patents
delay circuitInfo
- Publication number
- JPS59147328U JPS59147328U JP4012283U JP4012283U JPS59147328U JP S59147328 U JPS59147328 U JP S59147328U JP 4012283 U JP4012283 U JP 4012283U JP 4012283 U JP4012283 U JP 4012283U JP S59147328 U JPS59147328 U JP S59147328U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- diode
- delay circuit
- power
- switching diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の実施例を示すもので、第1図は第1の実
施例を示す電気回路図、第2図はタイムチャート、第3
図は第2の実施例を示す電気回路図である。
E・・・電源、SW・・・スイッチ、R1−R27・・
・抵LCI〜C5・・・コンデンサ、D1〜D6・・・
ダイオード、ZD・・・ツェナーダイオード、INV
l〜INV 5・・・インバータ、ムNDl・・・アン
ド回路、Bz・・・圧電ブザー、RY・・・リレー、T
R1・・・トランジスタ、sl、 s2・・・ブザーオ
フ点。The drawings show an embodiment of the present invention; Fig. 1 is an electric circuit diagram showing the first embodiment, Fig. 2 is a time chart, and Fig. 3 is an electrical circuit diagram showing the first embodiment.
The figure is an electrical circuit diagram showing a second embodiment. E...Power supply, SW...Switch, R1-R27...
・Resistor LCI~C5...Capacitor, D1~D6...
Diode, ZD... Zener diode, INV
l~INV 5...Inverter, MNDl...AND circuit, Bz...Piezoelectric buzzer, RY...Relay, T
R1...transistor, sl, s2...buzzer off point.
Claims (1)
デンサと、第1のCR時定数回路を介し接続されるバッ
ファアンプ回路と、電源投入時の電圧立と上がり時間を
規制するツェナーダイオードと第2のCR時定数回路及
び放電用ダイオードを介し接続されるインバータと、前
記バッファアンプ回路とインバータの出力側が共にHI
GH“状態になると出力を能動状態にするアンド回路を
構成するスイッチング用のダイオードと、該アンド回路
を構成するスイッチング用のダイオードに接続される負
荷回路とにより構成され、電源オン或いは電源オフ時に
一定時間だけ負荷回路を駆動するようにしたことを特徴
とする遅延回路。 (2)スイッチング用のダイオードをアンド回路とした
実用新案登録請求の範囲第1項記載の遅延回路。[Claims for Utility Model Registration] - (1) A power supply capacitor that is charged and discharged when the power is turned on and off, a buffer amplifier circuit that is connected via the first CR time constant circuit, and a voltage riser when the power is turned on. The Zener diode that regulates the rise time, the second CR time constant circuit, the inverter connected via the discharge diode, the buffer amplifier circuit, and the output side of the inverter are both HI.
It consists of a switching diode that makes up an AND circuit that activates the output when it enters the GH state, and a load circuit that is connected to the switching diode that makes up the AND circuit. A delay circuit characterized in that it drives a load circuit for only a certain amount of time. (2) The delay circuit according to claim 1, wherein the switching diode is an AND circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4012283U JPS59147328U (en) | 1983-03-19 | 1983-03-19 | delay circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4012283U JPS59147328U (en) | 1983-03-19 | 1983-03-19 | delay circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59147328U true JPS59147328U (en) | 1984-10-02 |
Family
ID=30170751
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4012283U Pending JPS59147328U (en) | 1983-03-19 | 1983-03-19 | delay circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59147328U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5521656A (en) * | 1978-08-02 | 1980-02-15 | Nissin Electric Co Ltd | Pulse generation circuit |
-
1983
- 1983-03-19 JP JP4012283U patent/JPS59147328U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5521656A (en) * | 1978-08-02 | 1980-02-15 | Nissin Electric Co Ltd | Pulse generation circuit |
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