JPS6352269A - Image processor - Google Patents

Abstract

PURPOSE:To reduce the overall scale of an image processing system by using a parallel image processor having an architecture suitable for transformation into LSI. CONSTITUTION:A parallel image processor 1 is connected to an image memory 2 via a data bus and an ITV camera 3 is connected to the memory 2 as an image input device together with a CRT monitor 4 which displays the contents of the memory 2. While the processor 1 and the memory 2 are connected to a control processor 5 via the data bus. The image information of the memory 2 is processed by the processor 1 and the result of this processing is stored in the memory 2 or the processor 5 which controls an image processing system as a whole.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing apparatus using a parallel image processing processor that performs local neighborhood image processing such as spatial product-sum operations.

Image processing processors process image data in parallel, as developed in the Pattern Information Processing System, one of the large-scale projects of the Ministry of International Trade and Industry (a collection of research and development results was published in October 1981). Many are trying to speed things up. However, since image data has a quadratic spread, it is difficult to process all image data in parallel. Therefore, local data in m rows and Xn columns of an image is often processed in parallel for calculations between neighboring image data, such as spatial product-sum calculations that express noise removal and contour extraction functions. Such locally parallel image processing is comprehensively explained in the above-mentioned literature or in the Trends in Image Processing Hardware by Masatsugu Kido (Information Processing Computer Vision Study Group Materials 86, September 1980). Except for the COD analog processing system, nothing has been made into an LSI. This is because it is difficult to convert a processor with a conventional architecture into an LSI in terms of the degree of integration and the number of pins. By incorporating the processor into an LSI, the double-column image processing device using the same can be made smaller.

An object of the present invention is to provide a parallel image processing device using a parallel image processing processor having an architecture suitable for LSI integration.

The present invention is characterized by: an image input device that inputs image data from the outside; an image memory that stores the image data from the image input device; an image display device that displays the contents of the image memory; at least one image data input port for inputting image data, n processor elements for image data calculation, and an arithmetic circuit for adding calculation results of these processor elements;
a parallel image processing processor comprising m basic modules installed in parallel, each having an output port for outputting the calculation result of the calculation circuit; and a management processor connected to and controlling the image memory and the parallel image processing processor. An image processing device comprising:

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 shows an example of a typical image processing system including an embodiment of the parallel image processing processor of the present invention. The parallel image processing processor 1 is connected to an image memory 2 by a data bus, to which is connected an ITV camera 3 as an image input device, and also as an image display device for displaying the contents of the image memory 2. CRT
Monitor 4 is connected. Further, the parallel image processing processor 1 and the image memory 2 are connected to the management processor 5 by a data bus. The image information in the image memory 2 is processed by a parallel image processor 1 and the results are also stored in the image memory 2 or provided to a management processor 5 that controls the entire system.

The parallel image processing processor 1 has a spatial product-sum operation as a typical image processing function. FIG. 2 shows an example of this local parallel processing. The pixel fIJ of the input image 6 and the sum-of-products weight 7 w14 are input to the parallel image processing processor 1, and the calculation result g here is output to the output image 8.

For example, image processing such as noise removal and contour enhancement is performed by multiplying the 4×4 pixel local image data fxx to f44 by predetermined loads W□1 to waa and calculating the sum.

FIG. 3 is a block diagram showing one embodiment of a parallel image processing processor applied to the parallel image processing system of the present invention.

This is an example of an image processing processor that processes local image data of 4×4 pixels, and is composed of four image processing processor basic modules 9A to 9D. The basic module 9A has four shift registers 10, and image data via these shift registers 10 is input to four processor elements 11 (PE#1 to PE#4).

These four processor elements 11 are given load data W11 to W14 from a load storage memory 12, and their outputs are input to an arithmetic circuit 13. The output of this arithmetic circuit 13 is input to an arithmetic circuit 14, and the output of this arithmetic circuit 14 is outputted from a data output port 15. Note that the calculation result data of the previous stage is input to the -1 calculation circuit 14 via the calculation result input port 16. Furthermore, the shift register 10
The input image data f14 input to the image data input port 17 is taken in through the image data input port 17, and the image data passed through the shift register 10 is outputted from the image data output port 18.

Next, the operation of the image processing processor 1 of this embodiment will be explained. The parallel image processing processor 1 includes an image memory 2
1 column of local image data (in Fig. 3, f11 to f4
4) The calculation results are applied in parallel and stored in the image memory 2. Input image data fl& is transferred to shift register 10
is input to the processor element 11 via the pixel fx4+ fzat fz
z+fxx are respectively input to the corresponding processor elements 11.

Pixel fxx is output from the image data output port 18 in case the size of the spatial product-sum operation is expanded to 4×4 or more. The processor element 11 is given the image data fi- to be processed from the shift register 10 and the load data W I J from the load storage memory 12, and performs multiplication. This result is given to the arithmetic circuit 13,
The calculation results of the four processor elements 11 are added. The output of the arithmetic circuit 13 is given to the arithmetic circuit 14, and the arithmetic result data from the preceding stage parallel image processing processor 1, which is input from the arithmetic result input port 16, is also input to the arithmetic circuit 14, and these are added to form data. Output port 1
5 outputs the addition result to the next basic module. In this way, by stacking the basic modules 9A to 9D in four stages, the g=Σfth W sa is output from the final stage basic module 9D. The processing contents of the parallel image processing processor 1 of this embodiment as described above are summarized in the time chart shown in FIG. In addition, gll in Figure 4
.

gtz represents the output of the parallel image processing processor 1 for each time Δ, and corresponds to g in FIGS.

According to this embodiment, the parallel image processing processor 1 is configured into a basic module 9A having four processor elements 11.
~9D, by adopting a configuration that processes local image data of 4×4 pixels, the number of pixel data input ports 17 and data output ports 15 are reduced, and the divided basic modules 9A and 9D are adapted to handle local image data. Since it can be arranged in a regular manner, the parallel image processing processor 1
This has the effect of making the architecture suitable for LSI integration.

As described above, according to the parallel image processing system of the present invention, since the image processing system uses a parallel image processing processor having an architecture suitable for LSI implementation,
The entire image processing system can be downsized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image processing system equipped with an embodiment of the parallel image processing processor of the present invention, and FIG. 2 shows an example of local parallel processing operations performed by the parallel image processing processor shown in FIG. 1. FIG. 3 is a configuration diagram showing one embodiment of the parallel image processing processor of the present invention, and FIG. 4 is a time chart showing the processing process of the parallel image processing processor of the present embodiment.

Claims (1)

[Claims] 1. An image input device that inputs image data from the outside, an image memory that stores the image data from the image input device, an image display device that displays the contents of the image memory, and the image at least one image data input port for inputting image data from a memory; n processor elements for image data calculation; an arithmetic circuit for adding the calculation results of these processor elements; A parallel image processing processor formed by installing m basic modules in parallel, each having an output port for outputting data; and a management processor connected to and controlling the image memory and the parallel image processing processor. Image processing device.