JPH0451873B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing apparatus using a parallel image processing processor that performs local neighborhood image processing such as spatial product-sum operations.

The image processing processor is part of the Pattern Information Processing System (1981), one of the large-scale projects of the Ministry of International Trade and Industry.
Many of them are attempting to process image data in parallel to increase speed, as is being developed in ``Research and Development Results Announcement Collected Papers Published in October 2019''.
However, since image data is characterized by a quadratic spread, it is difficult to process all image data in parallel. Therefore, local data in m rows by n columns of an image is often processed in parallel for calculations between neighboring image data, such as spatial product-sum calculations that express noise removal and contour extraction functions. . Such local parallel image processing is described in the above-mentioned literature or
Trends in image processing hardware, written by Masatsugu Kido (Information Processing Computer Vision Study Group Materials 86, 1980)
CCD
Nothing has been converted to LSI except for the analog processing system. This is because it is difficult to convert a processor with a conventional architecture into an LSI in terms of the degree of integration and the number of pins. By converting the processor into an LSI, the array image processing device using the processor can be made smaller.

An object of the present invention is to provide a parallel image processing device using a parallel image processing processor having an architecture suitable for LSI implementation.

The present invention is characterized by: an image input device that inputs image data from the outside; an image memory that stores the image data from the image input device; an image display device that displays the contents of the image memory; at least one image data input port for inputting image data, n processor elements for calculating image data, and an arithmetic circuit for adding the calculation results of these processor elements;
a parallel image processing processor comprising m basic modules installed in parallel, each having an output port for outputting the calculation result of the calculation circuit; and a management processor connected to and controlling the image memory and the parallel image processing processor. An image processing device comprising:

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 1 shows an example of a typical image processing system including an embodiment of the parallel image processing processor of the present invention. The parallel image processing processor 1 is connected by a data bus to an image memory 2, which includes an ITV as an image input device.
A CRT monitor 4 to which the camera 3 is connected also serves as an image display device for displaying the contents of the image memory 2.
is connected. Further, the parallel image processing processor 1 and the image memory 2 are connected to a management processor 5 via a data bus. The image information in the image memory 2 is processed by a parallel image processing processor 1, and the results are also stored in the image memory 2 or provided to a management processor 5 that controls the entire system.

The parallel image processing processor 1 has a spatial product-sum operation as a typical image processing function. FIG. 2 shows an example of this local parallel processing. The pixel f _ij of the input image 6 and the w _ij of the product-sum weight 7 are input to the parallel image processing processor 1, and the calculation result g here is output to the output image 8. For example, for 4×4 pixel local image data f ₁₁ to f ₄₄ , predetermined loads w ₁₁ to
Image processing such as noise removal and edge enhancement is performed by multiplying by _w44 and calculating the sum.

FIG. 3 is a block diagram showing one embodiment of a parallel image processing processor applied to the parallel image processing system of the present invention.

This is an example of an image processing processor that processes local image data of 4×4 pixels, and is composed of four image processing processor basic modules 9A to 9D. The basic module 9A has four shift registers 10, and these shift registers 1
Image data via PE#0 is input to four processor elements 11 (PE#1 to PE#4). These four processor elements 11 are given load data w ₁₁ to w ₁₄ from a load storage memory 12, and their outputs are input to an arithmetic circuit 13. The output of this arithmetic circuit 13 is input to an arithmetic circuit 14, and the output of this arithmetic circuit 14 is outputted from a data output port 15. Note that the calculation result data of the preceding stage is input to the calculation circuit 14 via the calculation result input port 16. Furthermore, the input image data _f14 input to the shift register 10 is input to the image data input port 1.
7 and the image data that has passed through the shift register 10 is output from an image data output port 18.

Next, the operation of the image processing processor 1 of this embodiment will be explained. The parallel image processing processor 1 is given one column of local image data (f ₁₁ to f ₄₄ in FIG. 3) in parallel from the image memory 2, and the calculation results are stored in the image memory 2. Input image data f ₄₄ is input to the processor element 11 via the shift register 10, but at this time, each pixel of adjacent pixels f ₁₄ , f ₁₃ , f ₁₂ , f ₁₁ is input to the corresponding processor element 11. Each is input. Pixel _f11 is connected to image data output port 18 in case the size of spatial product-sum operation is expanded to 4x4 or more.
is output from. The processor element 11 receives image data f _ij to be processed from the shift register 10 and load data from the load storage memory 12.
w _ij is given and multiplication is performed. This result is given to the arithmetic circuit 13, and the arithmetic results of the four processor elements 11 are added. Arithmetic circuit 1
The output of 3 is given to the arithmetic circuit 14, and to this arithmetic circuit 14, the arithmetic result data from the preceding stage parallel image processing processor 1, which is input from the arithmetic result input port 16, is also input, and these are added to the data output port. The addition result is output from 15 to the next basic module. In this way, the basic module 9
By stacking A to 9D in four stages, g=Σf _ij w _ij is output from the final stage basic module 9D. Parallel image processing processor 1 of this embodiment as described above
The processing contents are summarized in the time chart shown in FIG. Note that g ₁₁ and g ₁₂ in FIG. 4 represent the output of the parallel image processing processor 1 every time Δt, and correspond to g in FIGS. 2 and 3.

According to this embodiment, the parallel image processing processor 1
By configuring the basic modules 9A to 9D having four processor elements 11 to process local image data of 4×4 pixels,
The number of pixel data input ports 17 and data output ports 15 can be reduced, and the divided basic modules 9A and 9D can be arranged in a regular manner corresponding to local image data.
This has the effect of making it an architecture suitable for LSI implementation.

As described above, according to the parallel pixel processing system of the present invention, since the image processing system uses a parallel image processing processor having an architecture suitable for LSI implementation, the entire image processing system can be downsized. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image processing system equipped with an embodiment of the parallel image processing processor of the present invention, and FIG.
The figure is an explanatory diagram showing an example of local parallel processing operations performed by the parallel image processing processor shown in Figure 1,
This figure is a block diagram showing one embodiment of the parallel image processing processor of the present invention, and FIG. 4 is a time chart showing the processing process of the parallel image processing processor of this embodiment. 1... Parallel image processing processor, 2... Image memory, 9A to 9D... Basic module, 11...
Processor element, 13, 14... Arithmetic circuit, 15... Image data output port, 17... Image data input port.

Claims (1)

[Scope of Claims] 1. An image input device that inputs image data from the outside, an image memory that stores the image data from the image input device, an image display device that displays the contents of the image memory, and the image memory. at least one image data input port into which image data is input, n processor elements for image data operations, an arithmetic circuit that adds the arithmetic results of these processor elements, and an arithmetic result of the arithmetic circuit. a parallel image processing processor comprising m basic modules installed in parallel, each having an output port for outputting the image memory; and a management processor connected to the image memory and the parallel image processing processor to control them. Image processing device.