JPS6351778A - Screen display device - Google Patents

Abstract

PURPOSE:To attain the character display of the same size in both the horizontal and vertical directions by providing a clock generating means discriminating a 1st and 2nd horizontal synchronizing signals and switching them automatically into a 1st and 2nd clock frequencies. CONSTITUTION: A vertical synchronizing signal VD and a horizontal synchronizing signal HD are supplied to a horizontal synchronizing signal discriminating circuit 59 so as to discriminate whether the horizontal synchronizing signal is 31.5kHz or 15.75kHz and to output clock switching signals D, E representing the result of discrimination. The clock switching signal D is fed also to a vertical control circuit 55, and when the horizontal synchronizing signal HD is 31.5kHz, the horizontal synchronizing signal HD is counted by a binary counter, and when the count is an even number of times, a vertical address counter of the vertical control circuit 55 stops incrementing to generate a character signal corresponding to the address in the vertical direction twice. Thus, the size of the character in the vertical direction in case of HD=31.5kHz is made the same as that in case of HD=15.75kHz.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a screen display device for displaying character data, etc. on a television screen in a television receiver or the like.

(Prior Art) Conventionally, a television receiver has a horizontal scanning circle n of 15.
75KHz (1) Displaying a TV (-y revision) signal - There is an interlace scan display and a double scan display that displays a TV signal with a horizontal scanning frequency of 31.5KHz.

Figure 12 shows a CRT with a horizontal scanning frequency of 15.75 KHz.
(Cathode ray tube) This does not show a screen display device that can display characters on the screen, and the character signal generation circuit 21 for displaying the characters on the screen uses the horizontal synchronization signal 1-I of the input TV signal. D and square I'll (using No. 5 VD and the clock from the clock generation circuit 22, R (red),
Generates G (green), B (blue) character signals and YM (luminance) signals. The character signal generating circuit 21 determines the character display position on the CRT screen based on the horizontal synchronizing signal MVD. In this case, the vertical position on the CRT screen is determined by counting the horizontal synchronizing signal l-ID using the vertical synchronizing signal VD as the base flB, and the clock is generated using the horizontal synchronizing signal HD as the standard. By counting the clocks determined by circuit 22, the horizontal position is determined. Also,
The character signal generating circuit 21 is controlled by a control circuit 23 such as a microcomputer, and the data output from the control circuit 23 determines the character size, character pattern, etc. The RlG, B signals and YM multiplied signals output from the character signal generation circuit 21 are supplied to the RGB drive circuit 24, where they are superimposed on the R, G, B signals of the TV signal and output to the CRT 25. . The CRT 25 displays a character signal that is mR-modified to the TV signal.

By the way, the clock generation circuit 22 in the screen display device shown in FIG. If double scan display is desired with a TV signal, the design must be changed to increase the clock frequency by changing the oscillation constant of the clock generation circuit 22.

In other words, the conventional clock generation circuit for character signal generation is designed under the condition that the horizontal synchronizing signal is 15.75 KHz, and when the horizontal synchronizing signal is 31.5 KHz, which is twice the conventional value (double scan display). If used as is, there was a problem in that the horizontal character size displayed on both sides would increase approximately twice, and the vertical character size would conversely shrink to 1/2.

Therefore, when the same screen display device uses both the interlaced scan method (15°75 KHz) and the tuple scan method (31.5 KHz) as the horizontal scan method, characters with different clock frequencies are used for each. Signal generating means had to be provided.

(Problems to be Solved by the Invention) As described above, the clock generation circuit of the character signal generating means used for interlaced scan display where the conventional horizontal synchronizing signal is 15.75 KHz can be changed to
If used as is for KHz double scan display, there was a problem in that the horizontal size of the character signal would double and the vertical size would shrink to 1/2.

Therefore, the present invention is intended to eliminate the above problems.
Even if the horizontal synchronization signal is 15.75KHz, it is still 31.5KHz.
To provide a screen display device capable of displaying characters of the same size both horizontally and vertically on a screen even at KHz.

[Description of the Invention] <Means for Solving the Problems> The screen display device of the present invention displays characters based on a vertical synchronization signal and a horizontal synchronization signal of a first or second frequency included in a television signal. a screen display signal generating means for generating a screen display signal of a figure or a figure, and a means for generating a crotter for timing-controlling the screen display signal generating means, the means for generating a crotter that controls the timing of the screen display signal generating means, the first or second horizontal synchronizing signal A clock generating means that discriminates and automatically switches to a first or second clock frequency, and a screen display signal from the screen display signal generating means is mixed with the image signal of the television signal and transmitted to the CRT. The device is equipped with circuit means for outputting.

(Function) The present invention uses a horizontal synchronizing signal of a first frequency and a second frequency, which is twice the same, to operate a screen display signal generating means such as a character generator. The frequency of the clock supplied to the display signal generation means can be automatically switched in accordance with the first or second horizontal periodic signal, and the horizontal synchronization signal is 15.75KH2 and 31.
Characters of the same size can be displayed on the CRT in both the horizontal and vertical directions in either the 5th or 12th direction.

(Example) Hereinafter, the present invention will be explained based on the actual example shown in the drawings.

FIG. 1 is a block diagram showing an embodiment of the screen display device of the present invention.

In this figure, a TV signal received by an antenna 1 is supplied to a television receiver 2 (indicated by a dash-dot frame). The tuner 3 in the television receiver 2 receives the TV signal of the desired channel and also receives the video intermediate frequency signal (P
IF signal) and output. This PIF signal is amplified by a PIF circuit (video intermediate frequency amplification circuit) 4 at the next stage, and then supplied to an SIF circuit (audio intermediate frequency amplification circuit) 5, an RGB separation circuit 11, and a deflection circuit 14. The SIF circuit 5 extracts the SIF signal from the PIF signal and outputs the SIF signal from the PIF signal.
The F signal is supplied to the speaker 7 via the next stage audio amplifier circuit 6. In addition, in the RGB separation circuit 11, the PIF
The three primary color signals of R (red), O (green), and B (blue) and the YM (luminance) signal are separated from the signal, and these signals are sent to the next stage of R.
The GB drive circuit 12 mixes the signal with the character signal from the character signal generator 10 and outputs it to the triaxial cathode of the CRT 13. The character signal generator 1o has a horizontal scanning frequency of 15.
The character signal generating means is configured such that the clock frequency can be switched between 75 KHz and 31.5 KHz, and can operate based on a signal supplied from the control circuit 8. The control circuit 8 is a control means for the character signal generation device 10 including a channel selection circuit, and is a control means for the character signal generation device 10 including a channel selection circuit, and includes an input device 9 such as a keyboard.
A channel switching signal for performing a channel switching operation, etc. is input to the control circuit 2I+ circuit 8, and the control circuit 8 outputs a tuning voltage to the tuner 3, and at the same time outputs a tuning voltage to the character signal generator 10 to input the character size and character position. ,
Outputs a series of signals such as character type. The deflection circuit 14 includes a horizontal drive circuit and a vertical drive circuit, and extracts a horizontal synchronization signal qHD and a vertical synchronization signal VD from the PIF signal, and sends these signals to the character signal generator 10 and the RGB drive circuit 12. Along with adding
Horizontal and vertical deflection outputs synchronized with signals D and VD are supplied to the deflection yoke of the CRT 13. This deflection circuit 1
4 is also configured with specifications corresponding to cases where the horizontal scanning frequency is 15.75 Kf-1z and 1.5 KHz. The horizontal synchronization signal (ID) and vertical synchronization signal VD supplied to the character signal generator N10 are used for positioning the character signal.

FIG. 2 is a block diagram without showing the detailed structure of the character signal generating device 10. As shown in FIG.

In this figure, an automatic clock switching circuit 50 is connected to a clock oscillation circuit 51, and the clock frequency can be automatically switched between a horizontal scanning frequency of 31.5 KHz and 15.75 Kf-1z. has been done. The automatic clock switching circuit 50 transfers the basic clock Δ from the oscillation circuit 51 and this clock Δ to the countdown circuit 52.
The basic clock B whose frequency is divided into 1/2 is switched and outputted by a clock changeover switch 53, and the clock changeover switch 53 is connected to a horizontal synchronization signal discriminating circuit 597).
Switching is controlled by the clock switching signal E.

The five horizontal synchronization signal discrimination circuits are supplied with the bright signal VD and the horizontal synchronization signal HD, and determine whether the horizontal synchronization signal is 31.5 KHz or 15.75 KHz.
A signal E indicating the determination result is output.

The clock output C of the automatic clock switching circuit 50 is output to each subsequent stage circuit (input signal discrimination circuit 54, vertical control circuit 55, horizontal control circuit 56, and output control circuit 57), and each circuit is synchronized with this clock output C. It is operated by Further, the clock switching signal is supplied to the vertical control circuit 55 to control this circuit 55. On the other hand, a series of control signals such as character size, character position, character type, etc. are input from the control circuit 8 to the input signal discrimination circuit 54 of the character signal generating device 10. The input signal discrimination circuit 54 discriminates the control signal from the control circuit 8, outputs an address signal for determining the type of character to the character signal storage device 58, and outputs an address signal for determining the type of character to the vertical control 9 circuit 55. It outputs control signals for determining the vertical direction and vertical position of characters, and also outputs ai'l i2 for horizontal open circuit 56 to determine the horizontal size and horizontal position of characters.
Outputs n signal. The character signal storage device 58 is constituted by a character ROM, and stores a required number of character data constituted by a dot matrix of 5 dots 1 by 7 dots as shown in FIG. 3, for example. Is the vertical control B circuit 55 a character signal storage device? This circuit generates signals a to Q for reading the character data stored in the ff58 correspondingly in the vertical direction on both sides of the television receiver, and includes a clock switching signal, a vertical synchronizing signal VD, and a horizontal It is controlled according to the synchronization signal HD. Further, the output control circuit 57 is a circuit for reading character signals in parallel from the character signal storage device 58 and outputting them temporally in series, and the output character signals are RGB.
The signal is input to the drive circuit 12. The horizontal control circuit 56
is a timing signal circuit for generating character signals corresponding to the horizontal position of the television screen, and generates timing signals qh, i in synchronization with the horizontal synchronizing signal 1-ID.
This signal controls parallel writing and series reading of the output fan 1 to roll circuit 57.

In the above configuration, in the automatic clock switching circuit 50, the horizontal synchronization signal discrimination circuit 59 detects the horizontal synchronization signal 1-I.
When D is 31.5K)Iz, the clock switching signal becomes "1" and the clock switching signal F becomes "0". This signal provides the basic clock A h< as the output C of the clock changeover switch 53 and outputs it to each circuit.

Also, when the horizontal synchronization signal][''D is 15.75 KHz, the clock switching signal becomes 0'', and the clock switching signal E becomes II 1 +1.This signal causes the clock selection switch 53 to switch the basic clock B to each It is output to the circuit.

In addition, as shown in Figure 3, the character pattern consists of 5 dots per character, and the basic clock A
The relationship between the signal waveforms j corresponding to one dot of the character pattern displayed as ,B is as shown in FIG. That is, the basic clocks △ and B are synchronized at t and t, respectively.
', the width of one dot in the column direction (horizontal direction) is j,
2t and 2t' as shown in FIG. 2, and the width of one dot is determined by the frequency of B to the basic clock. In FIG. 3, the width of one dot in the row direction (vertical direction) is 047'5 for horizontal synchronization H.

The horizontal scanning frequency for each television reception is 31.
For double scan display of 5KH2, the character signal generator 10 is operated with basic clock A, and for interlaced scan display with a horizontal scanning frequency of 15.75KH2, character signal generator 10 is operated with basic clock B.

The vertical control circuit 55 generates the signal indicated by the arrow in FIG. 5 for interlaced scanning when the horizontal synchronizing signal QI-ID is 15.75 KHz. Further, when the horizontal synchronization signal (-IO) is 31.5 KHz, the signals shown in FIG. 6 are generated for non-interlaced scanning. Outputs Ja~9 or a'~q' in these signals
reads character signals corresponding to the rows of the character pattern shown in FIG. That is, the signal a corresponds to the first row, the signal b corresponds to the second row, . . . the signal 0 corresponds to the seventh row.

The above clock switching signal is also supplied to the vertical 11 control circuit 55, and when the horizontal synchronizing signal HD reaches 31.5 KH2, that is, when the clock switching signal is at zero level, the horizontal synchronizing signal)-ID is converted into a pinary counter. When the count is an even number [1], the incrementing operation of the vertical address counter of the vertical control circuit 55 is stopped, and character signals corresponding to the vertical addresses are generated twice. Can be done. Therefore, the size of characters in the vertical direction can be made as large as the same size when the horizontal synchronizing signal qHD=31.5 KHz as when HD=15.75 KHz.

Figure 5 shows the vertical synchronizing signal VD and the character-output signal Alki when the horizontal synchronizing signal HD is 15.75 KHz.
At this time, one-character readout signals shown at a-g are sequentially generated, and then character & output signals shown at a'-q' are generated sequentially at the end of the second vertical scanning period of 1V. The character pattern displayed thereby becomes as shown in FIG. In FIG. 7, the symbols ■~■ and ■'~■' in the row direction indicate horizontal scanning, and during the first vertical scanning period, ■→■→■→・
・・Character signals a-1, b-2°C-3, ・in the order of ■→■
..., f-6, Q-7 are generated, and in the second vertical scanning period, character signals a'-1, b' are generated in the order of ■'→■'→■'→...■'→■'. -2,c'-3゜..., f'-6
, a' -7.

Figure 6 shows the vertical synchronizing signal VD and character readout signal when the horizontal synchronizing signal HD is 31.5 KHz.
a-+ a'-+ in one vertical scanning period 1v
1)-11) ' -1-・-f -* f' -1g
Character read signals are generated in the order of -+g'. In this case, in Fig. 7, the horizontal scan is
■'→...■→■' is carried out in the order of character signal a-4.
, a'-1, b-2, b'-2,..., g-7, g
' Generate -7.

On the other hand, the horizontal control circuit 56
Assuming that the horizontal synchronizing signal of 2HD is 2HD, and the horizontal synchronizing signal of 31.5KH7 is D, then the horizontal synchronizing signal 2HD and the signal synchronized with HD, i and hr
, ir is generated. Signals 1 and h' are signals for the output control circuit 57 to write character signals read from the character signal storage device 58 in parallel with the horizontal synchronizing signals 2HD and 2HD in a certain relationship. signal i
, i' is the signal, and h' is the output control circuit 5.
This is a signal for reading out character signals written in parallel to 7 in series in time.

FIG. 8(a) 1 to horizontal synchronizing signal 2 (signal D).

FIG. 8(b) shows the relationship between horizontal synchronization signal 1-ID
FIG. 8(C) shows the relationship between the signals i' and i7, and FIG.
) and (b) show the character patterns displayed on the CRT screen in response to the signals shown in FIG. f, shown on signal 1,
f2. ..., f5 signal and f shown on signal i'
The signals 1', f2', . . . , f5' correspond to the 1st, 2nd, . As shown in Figure 8(b), 31.5
In the case of the horizontal synchronizing signal 1"D of KH2, the horizontal period is 1/2 compared to the case of the horizontal synchronizing signal 2HD of 15.75 KH2 as shown in FIG. Since this clock A is used and the frequency of the readout signal i' is also doubled, when characters are displayed on the CRT screen as shown in Fig. 8(C), the result is as shown in Fig. 8(a). 8th
The character width in the horizontal direction can be made the same as in the case of FIG.

FIG. 9 is a block diagram showing a detailed configuration of the automatic clock switching circuit 50 of FIG. 2. In FIG.

In this figure, reference numeral 108 is an input terminal for the horizontal synchronization signal HD, and reference numeral 109 is an input terminal for the vertical synchronization signal VD.

Then, the horizontal synchronization signal HD is processed by a binary counter 100.
The vertical synchronizing signal VD is input to the binary counter 100 for counting and clearing, and the signal VD is supplied to the D-type flip-flop [1 block 103].
is input as a clock. binary counter 1
00 counts the number of horizontal synchronizing signals HD in synchronization with the vertical synchronizing signal MVD, and outputs count outputs G, H, and I to outputs GQ7, Qa, and Q9, respectively. The count output G of the output terminal Q7 changes the logic level of "O" by 1° every time the horizontal synchronization signal HD is counted 64 times, and the output terminal Q
The logic level of the count output H of a changes every time the signal HD is counted 128 times, and the logic level of the count output 1 of the output rA Q 9 changes every time the signal HD is counted 256 times. The output signals qG and H of the binary counter 100 are input to an AND gate (AND gate i->101) to obtain an AND output J (J=GH).

This signal J is inputted to the next stage D-type flip-flop 102 as a clock. Also, binary counter 10
0 output signal, jTh l is horizontal synchronization signal 1-ID is 31
．． When the frequency is 5KHz, it is '1°', and when the frequency is 15.75KHz, it is input to the D-type flip-flop 102 as discrimination data that indicates 'O'. The data is output to the output QQQl and output as an output signal.

Further, the D-type flip-flop 103 at the subsequent stage takes in the data K using the vertical synchronization signal VD as a clock, and outputs a clock switching signal to the output Q2. A signal E, which is an inverted logical output of the clock switching signal, is outputted to the output terminal ζ2. The flip-flops 102 and 103 of the above type can be cleared by applying a DC voltage Voo. The output of the oscillation circuit 51 is input to the 3-state buffer 104 and the countdown circuit 5.
2 is entered. The countdown circuit 52 generates a second clock B by dividing the first clock A by two, and inputs this second clock B to the 3-state buffer 105 . These 3-state buffers 104. 'i
05, when the control signal is O, the output side becomes high impedance, and when the control signal is 1, the input signal is output to the output side.

The operation of the above configuration will be described with reference to FIGS. 10 and 11. Figure 10 shows the horizontal synchronization signal H
This is a waveform diagram when D is 31.5 KI-1z, and FIG. 11 is a waveform diagram when the leveler 191 signal HD is 15.75 KHz.

When the horizontal synchronizing signal HD is 31.5 KHz for double scan display, the binary counter 1 is displayed as shown in Fig. 10.
00 is from the fall of the vertical synchronizing signal VD to the horizontal synchronizing signal T
Start counting D and count 256 times, l-I
The D discrimination signal Ml becomes 1. The state of this ID discrimination signal I is output as a capture signal by the D-type flip-flop 102 at the rising edge of the clock J, and this signal is further inputted to the D-type flip-flop 103 in the subsequent stage by the clock of the vertical synchronization signal VD. The clock switching signal E is output from the D-type flip-flop 103. Therefore, the clock switching signal QD becomes "1", and the clock switching signal E becomes "011".

Also, when the horizontal synchronizing signal (D) is 15.75 KHz for interlaced scan display, the binary counter 100 starts counting the horizontal synchronizing signal HD from the falling edge of the vertical synchronizing signal VD as shown in FIG. 11, but only 256 times. Since it is cleared by the rise of the vertical synchronization signal VD before counting, the HD discrimination signal 1 remains 0, and the clock switching signal □t becomes ``011'', and the clock switching signal @E becomes ``1''.
become.

The O switch signal is as above, and E is 3-state buffer 1.
04.105 as a control signal, and the clock switching signal is outputted to an output terminal 107 connected to the vertical control circuit 55 in FIG.

When the horizontal synchronization signal 1-ID is 31.5KHz, the clock switching signal is "1'° and the clock switching signal E
Since is "'O", the 3-state buffer 104 is switched on and the 3-state buffer 105 is switched off, so that the first basic clock A is generated as the clock output C. Horizontal synchronization signal 1-ID is 15.75KH
When z, the clock switching signal is 'O'' and the clock switching signal E is 11111, so the second basic clock B is generated as a zero output C. In this way,
Automatic switching of clocks A and B becomes possible.

Although the embodiment shown in FIG. 1 describes a platform that superimposes character data on a TV signal, the present invention is not limited to character data, but also includes a circuit that generates data such as figures and symbols and superimposes it on a TV signal. It may be a configuration.

[Effects of the Invention] As described above, according to the present invention, the horizontal synchronization signal is
．． A screen display device that can display characters of the same size both horizontally and vertically on the screen using a single character signal generator by automatically switching the clock, regardless of whether the frequency is 75KHz or 31.5KHz. can be realized.

Therefore, it is possible to provide a video device for television reception and the like that is compatible with both interlaced scan display and double scan display.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the screen display device of the present invention, FIG. 2 is a block diagram showing the configuration of the character signal generating device of FIG. 1, and FIG. 3 is an explanatory diagram showing a display character pattern.
Figure 4 is a waveform diagram showing a clock signal and a signal corresponding to one dot in the horizontal direction of a displayed character, and Figure 5 is a vertical synchronization signal and character readout in the vertical control circuit when the horizontal synchronization signal is 15°75KHz. Figure 6 is a waveform diagram showing the vertical synchronization signal and character readout signal in the vertical υ control circuit when the horizontal synchronization signal is 31.5K)-1z, Figure 7 is the displayed character pattern. Figure 8 is an explanatory diagram showing the relationship between horizontal scanning and character signals. An explanatory diagram showing the relationship of signals in correspondence with characters displayed on a CRT screen. FIG. 9 is a block diagram showing the configuration of the automatic clock switching circuit of FIG. 2. FIG. FIG. 9 is a waveform diagram explaining the operation when the horizontal synchronization signal is 15.75 KHz. FIG. 11 is a waveform diagram explaining the operation in FIG. 9 when the horizontal synchronization signal is 15.75 KHz. It is a block diagram without showing. 8... Control circuit, 9... Input device, 10.
...Character signal generator, 11...RGB separation circuit, 12...RG8 drive circuit, 13...CRT, 14...Deflection circuit, 50
... Clock automatic switching circuit, 51... Oscillation circuit, 52... Countdown circuit, 53... Clock changeover switch, 54... Input signal discrimination circuit, 55... Vertical control circuit, 56...・Horizontal control circuit,
57... Output control circuit, 58... Character signal storage device, 59... Horizontal synchronization signal discrimination circuit, 100... Binary counter, 101... AND gate, 102.103... D type flip-flop, 104.
105...3-Stay 1 hepatuhua. DoT Figure 3 Figure 4 Figure 5 Figure 6 rl! J Figure 7 Figure 10 Figure 11

Claims (1)

[Scope of Claims] A screen display device capable of displaying an image on a cathode ray tube of a television signal having a first horizontal scanning frequency and a second horizontal scanning frequency doubled from the first horizontal scanning frequency, comprising: screen display signal generation means for generating a screen display signal of characters or figures based on a vertical synchronization signal and a horizontal synchronization signal of a first or second frequency included in the television signal; and this screen display signal. a clock generating means for generating a clock for controlling the timing of the generating means, the clock generating means being capable of determining the first or second horizontal synchronization signal and automatically switching to the first or second clock frequency; and the screen. 1. A screen display device comprising circuit means for mixing a screen display signal from a display signal generating means and an image signal included in the television signal and outputting the mixed signal to a cathode ray tube.