JPS6351667A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the areas of memory cells by a method wherein the neighboring memory cells are completely separated from each other by a high- concentration impurity layer coming into contact with the base parts of trenches, a depletion type MOS capacity is formed in the central part of each trench and an enhancement type MOSFET is formed on the upper part of each trench. CONSTITUTION:A MOS capacity for constituting memory cells is formed of an N-type epitaxial layer 22 grown on a P<+> Si substrate 21, first gate oxide films 26 formed on the internal surfaces of trenches 25 bored in this layer 22 and first gate electrodes 27 buried in through these oxide films 26. As this MOS capacity comes to be formed on a N-type semiconductor, it is a depletion type MOS capacity and as the trenches 25 are formed intruding into the P<+> Si substrate 21, the neighboring memory cells are completely separated from each other by the substrate 21. The N<+> diffused layers 24 of MOSFETs are connected to an Al film 28, which is used as a bit line, through contact windows 33 opened in an interlayer insulating film 32 formed on the N<+> diffused layers 23 and second gate electrodes 30 and the bit line does not affect the capacity of each cell. As the memory cells can be constituted in vertical type in such a way, the areas of the memory cells can be significantly reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor memory devices, particularly dynamic RAM.
(Randal ACCeSS M1311Or+/)
The present invention relates to the memory cell structure of .

BACKGROUND OF THE INVENTION Increasing the capacity of conventional dynamic RAMs has been achieved by reducing the area of the memory. However, in the Brainer-type cells conventionally used in large-capacity memories of 4M bits or more, the
It is impossible to secure the capacity of 0f[, and as an alternative structure, for example, I, E, E, E,
IEEE Transactions on El
ectron Devices), VolED-31,
No, 6. There is a trench structure memory cell described in P. P., P., 746-753.1984. Figure 2 shows CCC (Corrugated Capacitor).
13 is a cross-sectional view showing an example of a memory cell in a trench 41113m called 41113m. Memory cells up to CCC41'l are located in grooves (
a first gate oxide film 3 formed on the inner surface of the trench) 2;
and a first gate electrode 4 made of polysilicon doped with phosphorous and embedded in the trench 2 to form an MO8 type hanger. A gate oxide film 5 and a second gate electrode 6 forming a word line formed on the second gate oxide film 5 and a surface region of the p-type silicon substrate 1 on both sides of the second gate oxide film 5 are formed. n-type high f: i degree impurity diffusion layer (
An MO8 type field effect transistor (MOSFET) is formed by the n4'' layer) 7, and one side of the n'' layer 7, which becomes the source or drain of the MOSFET, is connected to the aluminum film 8, which becomes the pit line. 2 shown in
The first gate electrodes 4 of the memory cells are connected to each other and separated by a field oxide film 9 formed between the grooves 2 and a p-type diffusion layer 10.

11 is a memory cell formed in an adjacent column (not shown)
This is the gate electrode.

In Figure 2, the dimensions of groove 2 are 1 μm x 1 μm x 5 μm (
depth) and the thickness of the first gate oxide film 3 is 100 people, the surface area of MO88ffi is approximately 20 μg,
If MO8 capacity is 8, it will be about 691[.

As can be seen from this calculation example, a trench-structured memory cell has a small area (1 μm in the calculation example above) in a plan view.
This makes it possible to form a very large capacity.

Problems to be Solved by the Invention However, in the trench-structured memory cell described above, it is difficult to completely isolate the MO8O8 capacitance when the cell area is reduced. That is, field oxide film 9 and p
Although the current flowing near the surface of the p-type silicon substrate 1 can be prevented by the type diffusion layer 10, it is difficult to prevent the bunch-through current flowing inside the p-type silicon substrate 1 as shown by the arrow in FIG. Therefore, there is a problem in that memory malfunctions are likely to occur due to interference between the MO8 capacitors. On the other hand, when the impurity concentration of the p-type silicon substrate 1 is increased to prevent bunch through current, the pn junction capacitance connected to the aluminum film 8, which is the bit line, increases, so the bit line capacitance to cell capacitance ratio increases. There was also a problem.

The present invention solves the above problems, and provides a semiconductor device in which the MO8 capacitance of a memory cell is completely isolated, the area of the memory cell can be reduced, and the ratio of bit line capacitance to cell capacitance does not increase. The purpose is to provide the following.

Means for Solving the Problems In order to solve the above problems, the present invention provides: - an epitaxial layer formed on a semiconductor substrate of a conductivity type and having a conductivity type opposite to that of the semiconductor substrate; and an epitaxial layer formed on the epitaxial layer. a semiconductor surface layer of the same conductivity type as the semiconductor substrate, a drain region of a memory cell transistor of a conductivity type opposite to that of the semiconductor substrate formed on the half-half surface layer; a semiconductor substrate or a trench that is of the same conductivity type as the semiconductor substrate and is dug in the semiconductor surface layer and the epitaxial layer so as to reach the high concentration impurity layer of the semiconductor substrate; and a first insulator formed on the inner surface of the trench. a first conductive layer filled in the trench via the first insulating film, and a first region facing the semiconductor surface layer and the epitaxial layer, the first conductive layer facing the semiconductor surface layer; a second insulating film formed on the third insulating film, a third insulating film formed on the drain region and the first region; A second conductive layer is connected to the drain region through a contact window formed in a third insulating film on the drain region.

Operation With the above configuration, an isolation layer is formed by the high-fi impurity layer at the bottom of the trench, so the memory cells are completely separated, and a depletion type MIS capacitor is formed in the center of the trench. Since an enhancement type MISFET can be formed above the trench, it is possible to significantly reduce the area of the memory cell of the dynamic RAM.

Example Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 shows an embodiment in which a memory cell of the present invention is formed on a p+ type silicon substrate. In Figure 1, 2
1 is a p+ type silicon substrate, and p+ type silicon substrate 2
An n-type epitaxial layer 22 is grown on top of the n-type epitaxial layer 22.
A p-type diffusion layer 23 is formed on the type epitaxial layer 22 by an impurity diffusion method, an n+ diffusion layer 24 is formed as an S layer on the surface of this p-type diffusion layer 23, and a trench 25 is formed around the entire periphery of this n+ diffusion layer 24. In order to reach the p+ type silicon substrate 21,
The p-type diffusion layer 23 and the n-type epitaxial layer 22 are trenched.

an n-type epitaxial layer 22 grown on a MO8O8 capacitance ρ" type silicon substrate 21 constituting a memory cell;
The first gate oxide film 26 formed on the inner surface of the trench 25 bent by the n-type epitaxial layer 22 and the trench 2
Since this MO 88m is formed on an n-type semiconductor, the first gate electrode 27 and the n-type Even if the potential difference of the epitaxial layer 22 is 0, the MOS8 has a so-called depletion type MO8O8 capacitor in which an electron channel is formed. Further, since the trench 25 is formed by penetrating into the p+ type silicon substrate 21, adjacent memory cells are completely separated by the p+ type silicon substrate 21.

Next, the aluminum film 28 and MO8, which will become the bit line, are
A MOSFET that acts as a switch for controlling exchange of O8 capacitance charges faces the p-type diffusion layer 23 in a trench 25 dug in the p-type diffusion layer 23 formed on the n-type epitaxial layer 22 by an impurity diffusion method. A second gate oxide film 29 formed on the inner surface, an extreme R film 31 formed on the first gate electrode 27, and the second gate oxide film 2
It consists of a second gate electrode 30 serving as a word line buried in the upper part of the trench 25 via a gate electrode 9, and an n+ diffusion layer 24 formed on the surface of a p-type diffusion layer 23. The insulating film 31 serves to separate the first gate electrode 27 and the second gate electrode 30 buried in the trench 25.

Furthermore, MOSFET n+diffusion m24<in+expansion I&
It is connected to the aluminum film 28 which becomes the bit line via the window 33 to the contact 1 formed in the interlayer insulating film 32 formed on the layer 24 and the second gate electrode 30.
Bit lines do not affect cell capacity. As is clear from the cross-sectional views shown in FIGS. 1(b) and 1(c), the switching transistor of the memory cell according to this embodiment constitutes a vertical MOSFET, and the second gate electrode 30 has a voltage higher than the threshold voltage. Aluminum becomes a bit line when applied! 228 and a MO8O8 capacitor OSFET channel.

In this embodiment, the cells were separated using the p+ type silicon substrate 21, but it is also possible to separate the cells by forming a p+ diffusion layer on the bottom of the trench 25 by ion implantation. Of course.

Furthermore, in this embodiment, since the MOS FET is formed in the p-type diffusion layer 23 formed on the n-type epitaxial layer 22 by impurity diffusion, the impurity concentration of the n-type epitaxial layer 22 is limited to about 10 α or less. However, for example, if the n-type semiconductor layer that forms the MO8 capacitor is formed on a p-type substrate by an impurity diffusion method, and the n-type semiconductor layer on the surface is formed by an epitaxial method, the impurity concentration of the n-type semiconductor layer can be reduced. Approximately 1Q
It is also possible to set it to about -1.

In this way, since the memory cell can be configured vertically, the area of the memory cell can be significantly reduced.
Alternatively, since it is formed to reach the p+ diffusion layer on the surface of the silicon substrate, adjacent memory cells can be completely isolated by the p+ layer in contact with the bottom of the trench 25.

Effects of the Invention As described above, according to the present invention, adjacent memory cells are completely separated by a high concentration impurity layer in contact with the bottom of the trench, and a depletion type MIS capacitor is formed in the center of the trench. As a result, sufficient charge accumulation within the cell can be ensured. In addition, an enhancement type MOSFET can be formed in the upper part of the trench.
This has the effect of reducing the memory cell area. Also, the bit line capacitance to cell capacitance ratio does not increase.

[Brief explanation of the drawing]

FIG. 1(a) is a partial plan view of a semiconductor memory device showing one embodiment of the present invention, and FIG. 1(b) and FIG.
XX' and YY' cross-sectional views in FIG. 2A, and FIG. 2 is a cross-sectional view of a conventional trench-structured memory cell. 21...p+ type silicon substrate, 22...n type epitaxy. 23... p-type diffusion layer, 24... n+ diffusion layer, 25... trench, 26... first gate M film, 27... first gate electrode, 28... ...Aluminum film, 29...Second gate oxide film, 30...Second
gate electrode, 31... insulating film, 32... interlayer R
Membrane, 33... contact window. Agent Yoshihiro Morimoto Figure 1 21, -, A I+, Mini? 7 Mu Moon Official (Bi Ntra 4 N)
3θ -'+20 gout□呵l)nek (word wo Annnn 3)・-kon77t・Fig.

Claims (1)

[Claims] 1. an epitaxial layer of a conductivity type opposite to that of the semiconductor substrate formed on a semiconductor substrate of one conductivity type, a semiconductor surface layer of the same conductivity type as the semiconductor substrate formed on the epitaxial layer, and the semiconductor surface A drain region of a memory cell transistor of a conductivity type opposite to that of the semiconductor substrate formed on the semiconductor substrate, and a highly concentrated impurity of the semiconductor substrate or of the same conductivity type as the semiconductor substrate and the semiconductor substrate all around the drain region. a trench dug in the semiconductor surface layer and the epitaxial layer so as to reach the semiconductor surface layer; a first insulating film formed on the inner surface of the trench; and a trench filled with the first insulating film in the trench. a first conductive layer; a second insulating film that divides the first conductive layer into a first region facing the semiconductor surface layer and a second region facing the epitaxial layer; and the drain region. and a third insulating film formed on the first region, and a third insulating film formed on the third insulating film and on the drain region.
A semiconductor memory device comprising a second conductive layer connected to the drain region through a contact window formed in an insulating film.