JPS6351449U - - Google Patents
Info
- Publication number
- JPS6351449U JPS6351449U JP1986145367U JP14536786U JPS6351449U JP S6351449 U JPS6351449 U JP S6351449U JP 1986145367 U JP1986145367 U JP 1986145367U JP 14536786 U JP14536786 U JP 14536786U JP S6351449 U JPS6351449 U JP S6351449U
- Authority
- JP
- Japan
- Prior art keywords
- flip chip
- mounting structure
- wiring
- hole
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
- 238000005476 soldering Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Description
第１図は本考案の基板構造を示す図で、ａは正
面を示す図、ｂは断面を示す図。第２図、第３図
および第４図は、本考案にかかる実施例の断面の
図。第５図は従来の基板構造を示す図。 １……フリツプチツプ実装用基板、２……フリ
ツプチツプ実装部、３……貫通孔、４……フリツ
プチツプ、５……封止樹脂、６……真空、７……
密閉容器、８……圧空、９……デイスペンサー、
１０……外気との導通口。
面を示す図、ｂは断面を示す図。第２図、第３図
および第４図は、本考案にかかる実施例の断面の
図。第５図は従来の基板構造を示す図。 １……フリツプチツプ実装用基板、２……フリ
ツプチツプ実装部、３……貫通孔、４……フリツ
プチツプ、５……封止樹脂、６……真空、７……
密閉容器、８……圧空、９……デイスペンサー、
１０……外気との導通口。
Claims (1)
- 【実用新案登録請求の範囲】 はんだ突起電極（バンプ）を有する半導体素子
、以下、フリツプチツプと、配線を形成してなる
基板端子とを、はんだ接合する実装構造において
、 前記はんだ突起電極を有した前記フリツプチツ
プの能動面に、相対する配線を形成した基板部に
貫通孔を設ける事を特徴とするフリツプチツプ実
装構造。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986145367U JPS6351449U (ja) | 1986-09-22 | 1986-09-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986145367U JPS6351449U (ja) | 1986-09-22 | 1986-09-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6351449U true JPS6351449U (ja) | 1988-04-07 |
Family
ID=31056842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986145367U Pending JPS6351449U (ja) | 1986-09-22 | 1986-09-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6351449U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201707B1 (en) | 1998-05-28 | 2001-03-13 | Sharp Kabushiki Kaisha | Wiring substrate used for a resin-sealing type semiconductor device and a resin-sealing type semiconductor device structure using such a wiring substrate |
-
1986
- 1986-09-22 JP JP1986145367U patent/JPS6351449U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201707B1 (en) | 1998-05-28 | 2001-03-13 | Sharp Kabushiki Kaisha | Wiring substrate used for a resin-sealing type semiconductor device and a resin-sealing type semiconductor device structure using such a wiring substrate |