JPS63503581A - Device manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Device manufacturing method and thereby manufactured device Ezu Omega Hill 1. Moxibustion Gogong 1 The present invention generally relates to methods of manufacturing devices, such as semiconductor devices, and results. Regarding the device obtained as.

2. Skin Gogi I Metal-containing materials, i.e. pure metals, molecules or molecules containing one or more metal atoms. treated or treated of a type of material and/or a mixture containing one or more of the above; Deposition on unconventional substrates plays an important role in the fabrication of various devices.

These devices include, for example, conductor devices, integrated circuit devices, and magnetic Qi hub device included. Typically, for example pure metal treated or Deposition on selected areas of an unprocessed semiconductor substrate is a patterned deposition process. Forming a patterned photoresist layer on the substrate surface, followed by a deposition mask, e.g. Electron beam evaporation or RF sputtering of metal onto the surface of the substrate with the mask. This is achieved by Then removing the mask will reveal the selected substrate area. Only the metal cover remains. Alternatively, without forming a deposition mask, The metal is deposited directly onto the substrate surface using a patterned etch mask, e.g. , a patterned photoresist layer is formed over this metal. Next, metal or The etch mask is etched through the etch mask, the etch mask is removed, and the selected areas are Only metal is left behind.

There are many MOS ( (metal/oxide semiconductor) integrated circuit devices, e.g. n-channel MO3, p-chi channel MO3, and CMO5 (complementary MO5) integrated circuit devices.

(As used herein, integrated circuit refers to multiple interconnected discrete devices. do. ) These MO5 integrated circuits (ICs) typically include multiple MOSFETs. (Metal/Oxide Semiconductor Field Effect Transistor), each MOSFET is Semiconductor material 1 comprises an active surface layer of, for example, silicon. Individual MOSFETs are also A thin gate oxide (GOX) formed on the surface of the active layer ), for example, toped polycrystalline silicon formed on the surface of this GOX. (polysilicon) conductive gate, formed on both sides of this gate, MOSFET Contains two highly doped parts of the active layer that constitute the source and train , thick field oxide (FOX) (compared to COX) allows MOSFETs to It has the function of separating and electrically insulating.

The MOS IC described above extends from the source, train, and gate of the MOSFET. metal runner, e.g. aluminum or aluminium. Contains aluminum/copper alloy contacts through which electrical communication is established with the MOSFET. will be accomplished. These metal contacts and runners are deposited and patterned as described above. Formed using technology. That is, electrically insulating glass, e.g. Glass containing SiO□-P2O3 or SiO□-P2O3B2O3 is conventional or conventional chemical vapor deposition, CV D) Deposited on the MOSFET and FOX of the IC using technology. this is the gate A level filler (electrical insulation layer) between the metallization layer and the source/drain metallization layer. Then Il old man. Then this interlevel dielectric or source, train and gate patterned to form via holes. metal conductor, For example, aluminum or Deposited on the conductor between levels of the lever and in the path hole, source, train and gate Electrical contacts are made to the ports. Deposited Al (on the interlevel dielectric) patterned etch mask, e.g. Interconnect runners etched through the resist layer and terminating in contact butts or formed.

Importantly, the deposition of metal-containing materials onto device substrates often associated with undesirable interactions between the material and the substrate. For example, semiconductor materials, e.g. , silicon was deposited used for electrical contact to the source and train Shows high solubility in metals such as aluminum. In other words, silicon is aluminum tends to diffuse into aluminum and form aluminum/silicon alloys. others As a result, aluminum from the top metal contact is diffused into the bottom silicon and A substance called aluminum 5pike is formed. It will be done. As is well known, aluminum is a p-type dopant for silicon. Ru. Therefore, aluminum spikes can pass through an n-type source or train. (to a p-type substrate) at the source/substrate or train/substrate interface. The p-n junction is lost. Aluminum spikes are typically silicon Its presence is usually associated with the source and train This is not a major problem in devices where the p-n+1 coupling has a depth of about 1 gm or more. No. However, these spikes are due to the p-n connection, which is expected to be commercialized soon. This becomes a serious problem for devices where the depth of coupling is less than about tp.

Aluminum spikes are aluminum and silicon saturated aluminum/silicon alloys, i.e., saturated with silicon at the highest temperatures experienced during manufacturing. It has been proposed that this can be prevented or prevented by replacing it. (This alloy is Increasing the silicon concentration gradient at the interface between the aluminum and the source and train drop and thus the diffusion of silicon from the source and train to the metal contact. make it impossible. ) Unfortunately, after high temperature processing, i.e. at room temperature, this The alloy becomes supersaturated with silicon, and this makes the (aluminum-topped) silicon This results in precipitation of condensate. As a result of this precipitation, -t n source and train (typically toped to a level of 1019C11-3 or higher) metal contacts to - exhibiting contact resistance of cra2 or higher, i.e. undesirably high contact resistance. This will provide resistance. (In contrast, contours to p+ sources and trains (The resistance is only equal to or greater than about 10 ohm-cm.) Aluminum spikes provide a barrier to aluminum and silicon interdiffusion. This prevents high-resistance contacts by applying There are suggestions to avoid this. Furthermore, as this barrier, tungsten (W) It has been proposed to use One reason for this proposal is that tungsten patterned using one of two low-pressure CVD (LP(:VD) techniques). without using a deposition mask and without the need for subsequent etching. This is because it is known to be selectively deposited on the source and train. No. According to technique No. 1, tungsten hexafluoride (WF6) is routed into the interlevel dielectric. After the hole is formed and before the aluminum is deposited into this channel hole, it is processed. It is poured onto the silicon substrate-E. WF6 is compared to S　i　Oz of inter-level electric body WF6 is relatively inactive in the exposed source and train regions. W (solid) and (reaction chamber) are formed on these areas. (gas exhausted from) SiF4 is produced via the following chemical formula.

2WF6 + 3Si→2W + 3SiF4 (1) This reaction formula with removal of silicon from the rain (etching), which is negligible It was believed that it was a thing. Furthermore, the resulting tungsten layer typically has a thickness of approximately It has been reported that the layer is less than 15 nanometers (nm) thick, so this layer Too thin to act as an active diffusion barrier between aluminum and silicon.

In a second technique for selectively depositing tungsten, WF6 and H2 are flowed across the processed silicon substrate (all in the reaction chamber). The total pressure of the gas was previously kept at about 1 ton). First, the saw where WF6 was exposed. The zero-order reacts with the Si of the trains and trains to form a thin layer of W (as explained above). Exposure is performed under the condition that the deposition temperature is approximately 250°C or higher and approximately 6006°C or lower. W or W to cover the source and train regions but not the interlevel dielectric SiO. It acts as a catalyst to promote the chemical reaction between F6 and H2, and through the following chemical formula (so additional W (formed on the base and train) and 11F (exhausted from the reaction chamber). gas).

WF6+ 382-+ W+ 511F (2) The second technique is an effective diffusion barrier gives a sufficiently thick layer of tungsten to act as Aluminum contacts to p source and train regions (covered with W) is a contact resistance that is too high, i.e. a contact of about 10 oh+*-cm2 or more. It has been reported that it shows some resistance. (N source and tip with a depth of approximately 1gm) The contact resistance to the rain is greater than or equal to approximately 110-5oh-cm2. (reported to have low resistance).

In other words, as an unrealized problem for those involved in the development of device manufacturing methods, , treated or untreated bases that avoid the problems associated with the methods listed above. Techniques for depositing metal-containing materials onto plates remain to be developed.

& DanyΣ4 Leopard The present invention provides at least two entities in one region of a treated or untreated substrate. A reaction step to form a metal-containing material over a region, multiple regions, or all regions. The present invention relates to a device manufacturing method including a chip. In many cases, this desired reaction is One (or more) of these reactive entities and the substrate material 1, e.g. Semiconductor materials (found on untreated substrates), metals (found on treated substrates) , or with a second reaction between S102 (found on the processed substrate) ( (It may even come before this second reaction). What is important is that this second reaction now This has very undesirable consequences that have not been recognized until now. For example source and the reaction given in equation (2) to form W on the silicon surface of the train If you want to react WF6 and H2 according to reacts with silicon according to the reaction that occurs, and for this purpose the source and train are partially erode. This erosion has been believed to be insignificant, or The extent of erosion of p sources and trains is usually much greater than that of p sources and trains. A crab dog was discovered. In fact, an n source with a depth of about 1 gm or less and Trains are often severely eroded, sometimes almost completely eroded. It was discovered that it can move. In addition, it has a depth of approximately 1 pm or less (covered with W). - and n Aluminum contacts to source and train The resistance has a depth of about 1 μm or more, which has been reported so far (covered with W). ) is much higher than the contact resistance to p and n+ sources and trains. It's been found. For example, a p source (covered with W) with a depth of about 1 well or less and the contact resistance to the train is approximately 5 x 10 ohm-cm2. Something was discovered. In addition to this, the stomach is covered with a depth of about 1 μm or less. )n Source and contact resistance must be approximately 10 oh+m-cm2 or more It's been found.

The device manufacturing method according to the invention differs from the prior art method and the second (undesirable) ) Various techniques can be used to prevent or significantly reduce the magnitude of adverse effects associated with reactions. They differ in that they include techniques. that is, the substrate material and at least two reactive entities. The rate of the (undesirable) reaction between one (or more) of the at least two reactions In order to suppress the rate of (required) reactions between reactive entities without significantly reducing them, A new technology has been developed. For example, we want to react WF and H to form W. In the case of 1. without significantly reducing the reaction rate between WF6 and H2.　W　F　6 and Si (associated with undesirable reactions), e.g. increasing the concentration of one of the products of a reaction, i.e. the concentration of S i F, s can be significantly reduced by increasing (above the normally occurring concentration) Something was discovered. With this technique (and others) n and p+ sources and Both erosion and rain are greatly reduced. This corrosion reduction is approximately 1fi1.11 or more. This is particularly important in devices with source trains of n depth. Furthermore , quite unexpectedly, the commands to both n and p sources and trains The contact resistance has also dropped significantly to a level below approximately 110-6oh -0m2. give good results.

Figure 1 μΣ Emperor No. 1. group FIGS. 1 to 7 show diagrams included in one embodiment of the device manufacturing method according to the present invention. and FIGS. 8 to 10 illustrate the prior art manufacturing method and Device contact resistance achieved using the device manufacturing method according to the present invention show.

1 Seed Oni Eitomo The invention relates to devices such as discrete semiconductor devices, integrated circuit devices, and bubbles. Regarding the method for manufacturing bubble devices, the method includes metal on one area, multiple areas, or the entire substrate that has not been processed. forming a containing material. The invention also results from the method according to the invention. Regarding devices.

According to the invention, the formation of the metal-containing material comprises at least two (other than the substrate material) This is accomplished by reacting reactive entities. Here, at least this entity The other includes metals of the type contained within the metal-containing material. As explained, this A reaction between at least two reactive entities often involves one of the reactive entities ( a second reaction (or series of reactions) between the substrate material (or reactions) and the substrate material. This too As explained above, this second reaction is usually a previously unrecognized highly desirable phenomenon. give undesirable results. To avoid or increase this undesirable result, In order to reduce the One (or more) of various techniques may be used to slow down the reaction associated with the It will be done. Importantly, these techniques greatly reduce the rate of reaction between two reactive entities. Selected not to be lowered. (For the purposes of this invention, a large reduction in this reaction The problem below could be avoided when the rate of formation of the metal-containing material was about 0.1 n/min or higher. It is considered as ) Some of the techniques listed above are different from those traditionally used (reaction chamber using a different total pressure (of the gas in the chamber) or using a different reaction temperature than traditionally used. one or more products (generally (from normal) with a change, e.g. an increase. Which technology to use in a particular situation control samples should be used to determine whether the

- As an example, the silicon surface of the MO5FET source and train, as explained above. When reacting 1i9F6 and 112 to form W on top, inevitably WF6 also reacts with silicon and erodes the source and train. n Sauce and tray The extent of the erosion of the train is much larger than that of the p source and train. In fact, on As explained, n sources and trains with a depth of less than approximately 1 inch are severely eroded. 1 Usually almost all eroded 0 For purposes of this invention, the source or train The depth is a least-squares corrected plane approximation value (least-square) to the original substrate surface. es-fit planar apporoxi-mation) source or is the lowest dopant concentration in the train equal to the dopant concentration in the surrounding substrate It is defined as the length of the vertical extension extending to a point. This point is, for example, S IMS analysis or traditional junction staining techniques Therefore, it is determined. Regarding these coloring techniques, for example, W, E, Beadle (W , E., Beadle) etc. gy), John Wiley and Sons 5ons % New York, 1985 section 5-9). and.

Furthermore, as mentioned above, the reaction rate for the undesired reaction between WFs and Si is For example, the concentration of undesired reaction products, i.e., the concentration of 5IF4 (normally occurring) can be easily dropped by increasing n It has been discovered that over-etching of sources and trains can be reduced. Si As the concentration of F4 increases, the desired effect increases. However, S iF 4 There is a tendency for the reaction rate between wF6 and 82 to decrease as the concentration increases. Therefore, According to the invention, 91F6 and H2 are added to the reaction chamber, e.g. C! l (standard cubic centimeters perm inute) and 2000SCC1 at a flow rate of 81 at a flow rate in the range of about 1 sec to about 101005e This is undesirable because it kills the response rate reduction effect. Approximately 100sec+slu upper SiF The flow rate of 4 is undesirable because it greatly reduces the reaction rate between Koreka wF6 and H2. .

In addition, the total pressure inside the reaction chamber was raised above the conventional level of 133 Pa (1 Torr). It was also discovered that the reaction rate between WF6 and Si decreased. In addition to this , the use of reaction temperatures outside the conventional temperature range, e.g., temperatures below about 250 degrees C. and temperatures above about 600 degrees Celsius give similar desirable results. However, approximately 600 degrees Temperatures above C drop the selectivity in the formation of W.

The technique described above is not only effective in forming W, but also applies to a wide range of metal-containing materials. It is also effective in forming materials. For example, molybdenum, tantalum, titanium and Metals such as rhenium and their corresponding silicides are is a chloride, for example, M　o　F　a, T　a　(l　sTiα4, and ReF 6 is reacted with a reducing agent, e.g. H2 (to produce metals) or 5IH4 (to produce silicides). can be easily generated by responding. As mentioned above, these metal fluorides or Chlorides tend to react with silicon and give the undesirable results described above, provided However, these undesirable reactions and associated reaction rates can be easily determined using the techniques described above. It is possible to drop it to

As an academic aspect for a more complete understanding of the present invention, the following two non-challenges may be helpful: Including 71/MO3FET? MO3IC1 For example, n-channel MO3IG Alternatively, the application of the device manufacturing method according to the present invention to the manufacturing of CMO3IC will be described. . Importantly, this n-channel MO5FET can be Includes source and train. Additionally, this MOSFET can be used for source and tray Aluminum and silicon interdiffusion (interdiffusion) at Diffusion barriers to prevent or reduce, including, for example, tungsten diffusion barriers, Aluminum or these sources and birds. Spike through In (5pik) prevent from doing.

As shown in FIGS. 1 to 7, according to the present invention, n-channel MO3F MOS IG containing ET is a thin GO layer on the surface of a layer of toped semiconductor material 20. The 0 layer 20 manufactured by forming a thick FOX 40 with a semiconductor constitutes the surface active layer of the substrate IO of body material. MOS IC or n-channel and p - When containing both channel MO3FETs, the substrate 10 is necessarily of p-type and Includes both rotary and bulk regions. In the following description, n-channel The MO5FET is, for example, a p-FET with a doping level of 1016c11-3. Assume that the type is manufactured in the bulk area.

The thick FOX 40 covers the MOSFET or COX to be formed on the surface of layer 20. GASAD (gate-and-source-and-drain) territory The region 50 is separated. For example, if the active layer 20 is silicon, GOX 30 and FOX 40 typically have thin and thick layers of It consists of For example, FOX 40 can thermally oxidize the surface of layer 20. formed by. F to expose GASAD region 50 on the surface of layer 20. After opening the window in the OX (by conventional techniques), the GOX 30 or e.g. layer 2 It is formed by thermally oxidizing the surface of 0 again. For example, VLSI (ver y large 5cale integrated) In the case of MO5IC, The thickness of 5iOz GOX 30 ranges from about 1 Snm to about ]00nm, Preferably, it is about 2On+i. GOX 30 with a thickness of about lSnm or less is The thin layer of dielectric breakdown This is undesirable due to the risk of causing On the other hand, if it is thicker than about 100n*, Undesirable because device operation requires unnecessarily high voltages.

The thickness of SiOz of MOS IC ranges from about 200nm to about 80On11. and preferably about 400 nm. Thicknesses of approximately 200 nm or less are lanner ( The voltage applied to the runners may reverse the underlying semiconductor material. . On the other hand, thicknesses of about 800 nm or more are such that such a thick layer is not suitable for subsequent metals, e.g. , is undesirable because it makes a well-compliant deposition of aluminum difficult.

After GOX 30 and FOX 40 are formed, a layer of gate material N1, e.g. A layer of silicon is deposited on GOX as well as FOX and then (by conventional techniques) ) is patterned to form gate 60. Deposited gate material thickness , Therefore, the gate thickness is preferably in the range of about 200 nm to about 80 [1 nm]. Preferably, it is about 600 ns. Such a thin layer with a thickness of about 20 nm or less has an undesirably high sheet resistance and an interlevel dielectric (1nterlevel Etching of via holes through dielectric There is a risk of excessive erosion during maintenance. This kind of thickness is about 800 nm or more. Achieving substantially vertical gate sidewalls can be difficult when etching thin layers. undesirable.

Using gate 60 as a deposition mask, dopants are deposited into active layer 20 on the opposite side of the gate. (This will later be applied to the active layer 2 to form the source and train of the MOSFET. 0) or injected. It is an n-channel MO3FET, and the active layer 20 is, for example, (p-type) silicon, then the effective (n-source and Examples of dopants (for forming trains) include phosphorus, arsenic, and arsenic. Contains a lot of things. Furthermore, the radiant energy of these dopants (incid ent energies) is in the range of approximately 10 keV to 300 keV, and is preferably Preferably, it is about 100 keV. Energy below about 10 keV is the result. This is undesirable because the joint is too shallow. Energy over 300keV In this case, the resulting bond becomes too deep. In other words, after diffusion, a depth of more than 1 μm reach.

If the MOS IC also includes a p-channel MO5FET, for example, 1110s I If it is a CMO3IC, the substrate 10 is a typical driver of about 1016C11-3. - with a punt level (in which a p-channel MO3FET is formed) -Type Includes bulk area. Later, the source and trench of the p-channel MO5FET low type bulk region to form an in, e.g. n-type silicon Effective p-type dopants to be implanted into the active layer of Includes minium, and gallium. The radiant energy of these dopants is Usually the same level as above.

Interlevel dielectric 70 then FOX 40, gate 60, and GASAI area 5 0 doped portion. Examples of the interlevel dielectric 70 include For example, does it include Sin, -P2O5 or 5in2- P2O5-B2O3? , these materials are easily deposited using conventional CVD techniques. Interlevel dielectric 7 The thickness of 0 ranges from about 172 mm to about 2 gm, preferably about 1 uL+* It is said that If the thickness is less than approximately 172 μm, such a thin layer will not provide sufficient insulation. undesirable for. With a thickness of about 2wl11 or more, such a thick layer During subsequent metallization, the step cover will not work properly.

The top side of the deposited interlevel dielectric 70 is typically not flat (this is due to (usually a problem in later processing). Deriving the fluidity of the interlevel dielectric 70 , therefore, to achieve surface flatness as well as the implanted dopants in the active layer 20 to form the source 80 and train 90. Approximately 1 hour to 2 hours at temperatures ranging from 0 degrees C to approximately 1100 degrees C. It is heated only for a certain period of time. When heated at a temperature of about 850 degrees C or less and for about 1 hour or less This is not desirable because the amount of glass flowing is too small. On the other hand, about 110 Temperatures above 0°C and heating times longer than approximately 2 hours may result in undesirable deep bonding. There is a risk that it will form.

After the formation of the source and train, the interlevel electric current is applied to the source, train, and gate, respectively. to drill passage holes 100, 110, and 120 (using conventional techniques). pattern). source, train and gate (to be formed after ) If aluminum is used as the electrical contact and the substrate IO or silicon , over each source and train to prevent aluminum and silicon interdiffusion. A barrier (130, 140) is formed. At the same time, a layer 150 is formed on the gate 60. It is formed. The diffusion barrier includes, for example, a region of tungsten. as an alternative , this barrier may contain regions of titanium, tantalum, molybdenum or rhenium. I can bring it. The thickness of the diffusion barrier is preferably in the range of about 30 nm to about 150 nm. In other words, it is about 1100n. Thicknesses of approximately 30n or less are required for such thin areas. Undesirable as it gives a diffusion area that is too weak. For thicknesses of about 150 nm or more, Selectivity in the formation of tungsten will be lost.

If the diffusion barriers 130 and 140 are tungsten, the effective thickness of tungsten By reacting WF6 and H2, it can be easily and selectively applied to the source and train. It is formed.

Furthermore, in order to suppress excessive etching of n sources and trains, excessive S iF will be introduced. The flow rate of WF6 is in the range of about 1 SCC [l to about 30 sec. and preferably about 1105ecI. At flow rates below about 4 sccrn , the tungsten formation rate becomes too slow. On the other hand, a flow of about 30 sec + 1 or more The sooner the equipment used to form the tungsten becomes more corroded, the less desirable it will be. Not.

The flow rate of H2 is in the range of about 101005e to about 5000 seconds, preferably is approximately 2000 sec+o. Flow rates below about 100 SCC11 indicate excessive syringe. This is undesirable because it causes recon erosion. A flow rate of approximately 5000 sec+a or higher is desirable. This results in an undesirably high total pressure.

The flow rate of S Preferably, the number of layers is about 20 scc. Approximately 1sec or less and approximately 100sCCI1 or more Flow rates above are undesirable for the reasons stated above.

The total pressure of the gases used in selective formation ranges from about 13 Pa (100 mTorr) to The range is approximately 267 Pa (2) Torr, preferably approximately 133 Pa (1 Torr). Saru. In addition to this, the reaction temperature ranges from about 250 degrees C to about 500 degrees C. , preferably about 300 degrees Celsius or about 550 degrees Celsius.

Total pressure of about 13 Pa (100 millitorr) or less and reaction temperature of about 250 degrees C or less is undesirable as it gives a low tungsten formation rate. Approximately 267 Pa ( Total pressures above 2 Torr) provide gas-phase nucleation of tungsten and Reaction temperatures above about 600 degrees Celsius, which are undesirable because they do not give rise to nucleation on the surface. In this case, selectivity in tungsten formation is lost.

After the formation of diffusion barriers 130 and 140, a layer of metal 160, e.g. on the layer or interlevel dielectric 70 and through the sources, trains and gates. deposited in the pores. The thickness of layer 160 ranges from about 1/2 gm to about 2 gys. Ru. Thicknesses below about 1/2 p-rrr give undesirably high sheet resistance. With a thickness of approximately 2p, ra or more, such thick layers may be difficult to pattern when patterning this layer. Substantially vertical sidewalls become unattainable. Following the deposition, metal contact batts The metal layer 160 is patterned to form interconnect metal runners terminating in the (not shown), e.g. selective reactive ion etching. This is how it was processed The substrate is then subjected to reactive ion etching to remove radiation damage caused during etching. For example, the material is annealed at a temperature of 450 degrees Celsius for about one hour.

MOS IG or completed by a series of conventional steps or these steps The moisture and physical A silicon nitride layer is deposited on the IC to form a barrier to protect it from physical damage. be done.

The MOS IC described above differs from the conventional MOS IC by forming or substantially invasive diffusion barriers. It differs in that it provides non-food n sauce and train. (For the purposes of this invention The source or train is a diffusion barrier derived from a least-squares corrected plane approximation of the original substrate surface. The vertical extension to the lowest point of the interface between the wall and the source or train is approximately 30 nm or less). In addition to this, What was completely unexpected was that the source of the n-channel MO3FET and All sources and trolleys of this IC including train The metal contact to the rain is about 10 ohm-cm2 or less, typically about 5x Importantly, this The unexpectedly low contact resistance is due to thermal stability, i.e. It is substantially unaffected by conventional annealing procedures. For this reason, the conclusion The resulting contact resistance is stable against heat, something that has never been possible until now. much lower than the level. (For the purposes of this invention, source or train The contact resistance to the source or train is the contact resistance Rc to the source or train, and the contact resistance Rc to the source or train. It is taken as the product of the area A of the upper surface of the train. The former is a data containing a source or a train. By measuring the current-voltage (1-V) curve across the area of the device board. You can easily decide.

The depth of the source or train to the area of the upper surface is 4 or more, then using conventional techniques, e.g. Scanning electron microscope, transmission electron microscopy, or secondary ion mass spectrometry Measured using a microscope. Next, based on the measurements of A and 4, the source or If the ideal curve 1-V for the train is, for example, S, M, , :C, Suze(S, M, 5ze), Device embedding (Physics of 5esiconduc) tor Devices), John Willie Ant Sands (John W iley and 5ons, N.

Y, ), 2nd edition, page 304. Typically, the measurement The determined I-V curve deviates from the theoretical I-■ curve by a certain amount.The important thing is that , Re has a certain relationship with this deviation. In other words, Rc=muV/l Therefore, it is expressed as Here, △V is between the two I-V curves for a fixed current ■ represents the difference in voltage values.

Alternatively, Rc applies a forward bias voltage between the sources or trains; As we increase this, we get the corresponding dV/old, the result of the applied voltage. easily determined by measuring the derivative with respect to the source/train current I'll come. The contact resistance is saturated, i.e. with increasing dV/di or forward bias. It is equal to dV/cl+ at the time when both stopped changing.

Although not essential to the invention, the above MOS IC is preferably expanded as described above. A region of metal silicide, i.e. core, is placed on the source or train before forming the diffusion barrier. Baltic silicide, titanium silicide, platinum silicide, or molyfden Manufactured to contain silicides. These metal silicide regions result in low Source and train of MOS IC including source and train of channel MO3FET This is important for providing stable contact resistance to heat to the rain. obtained in this way The resulting contact resistance will be even lower than the values discussed above. That is, about 10 oh m-cm2 or less, and further, about 10 ohm-cm2 or less. metal silicide thickness The thickness is in the range of about 30 nm to about 1100 nm. Thickness less than approximately: lOnm, A layer this thin usually penetrates into the overlying metal or substrate, resulting in contact resistance. This is inappropriate because it does not prevent the increase in Thickness of approximately 1100n or more , such a thick layer consumes an unreasonably large amount of substrate material during silicide formation. It is not appropriate for this purpose.

Preferably, the metal silicide region has a corresponding pure metal level within the solid body. Depositing, i.e., rf-sputtering, into the via holes and then exposing to an inert atmosphere, e.g. sintering in the Rougon, thus causing the metal to react with the source and train silicon. formed by The thickness of the deposited metal is about 15 nm to about 50 nm. range. Thicknesses of approximately 15 nm or less and approximately 50 nm or more are within the scope of the above description. This is undesirable because it gives the metal silicide a thickness that is out of range. Appropriate sintering temperature , and the corresponding sintering times range from about 1 hour at about 300 degrees C to about 1000 degrees C. The duration is approximately 1 hour. Sintering temperature of about 300 degrees C or less and sintering of about 1 hour or less The time is not suitable as the reaction between the metal and silicon will be incomplete. Approximately 11 A sintering temperature of 00 nC or more and a sintering time of about 1 hour or more will reduce the amount of gold in the metal silicide. suitable for causing undesirable reactions between both silicon and silicon dioxide. Not true.

Using the sintering procedure described above to form metal silicide regions, the source and Some erosion of and cane occurs. However, this erosion usually occurs between WF6 and the source. compared to erosion produced by undesirable reactions between silicon and train. It's small.

Importantly, this metal silicide region is porous and therefore free of reactive entities, For example, WF6 can react with and attack silicon in the source and train. forgive.

Additionally, WF6 has a tendency to leach and react with silicon in metal silicides. others Therefore, the method according to the invention described above prevents the attack of metal silicides and substantially eliminates the attack. No source and train is required to achieve this. (For the purposes of this invention The diffusion barrier and the metal silicide covered source or train are Lowest point of interface between metal silicide and source or train from imaginary plane Substantially no erosion is considered when the length of the extension is less than about 30 nm. child The virtual plane of is below (within the substrate) the least squares correction approximation plane to the original substrate surface. located parallel to this. In addition to this, the vertical length extending between these two planes is equal to the thickness of the corresponding uniform layer of silicon consumed to form the silicide stomach.

This thickness can be easily inferred from the amount of metal within the metal silicide, which can be determined by e.g. Rutherford Back-5catt It can be easily determined using the ering technique. used to form metal silicides If the source or train is not a silicon source or train, the virtual plane is on the original substrate surface. It is the same as the least squares corrected plane approximation value for. ) example Two groups of silicon wafers of opposite conductivity types were processed as follows. It was. Here, the first croup, called groupe, has a resistance of 20-100Ωca. Contains 25 p-type wafers exhibiting resistance, here referred to as group ■ The second group consisted of 25 n-type wafers exhibiting a resistance of 10-20Ω. It was composed of

First, a silicon dioxide layer with a thickness of approximately 1 On- is thermally deposited onto an individual wafer. The grown zero-order relatively heavily doped n-type bulk region or group n-ties formed in a wafer with a relatively high concentration of doping It is formed in the bulk region of the group H or within the wafer of the group H and is incorporated into the CMOS device. The p-tab and n-tab used were simulated. This glues boron ions 7' I (1) Ux-honey injection L/ (30keV, 4X 1012cm-2) , ') ions were implanted into group H wafers (100 keV, 2 x 10 12c111-2) shi, next niu x-ha’j: Heating at 11flO degrees C for about 2 hours This was achieved by diffusing it into the wafer.

A layer of silicon nitride with a thickness of approximately 120 no+ is deposited using conventional LPGVD techniques. Loop I and Group II were deposited on individual wafers. on individual wafers The silicon nitride layer was then selectively reactive ion etched in an atmosphere of CHF3 and 02. . Deposition of individual wafers of field oxide (FOX) with a thickness of approximately 600 nm. Thermal growth was performed on the exposed surface area as a result. Removed silicide nitride Later, a gate oxide (GOX) with a thickness of about 25 nm is pre-layered with silicon nitride. was thermally grown on individual wafers with surface areas covered by .

The ultimate formation of what will result in source and train regions within the wafer Therefore, Groupe's wafer is from axio C1l to ix 1016cm -100 keV arsenic (n-type dopant) at various dose levels in the range of -2 injection). Arsenic passed through the area covered by GOX, but FO The area covered by X was not reached. Similarly, 8x Various dose levels ranging from 101 family layer-2 to 1 x 1016clI-2 50 keV boron-difluoride (p-type dopant) implantation was performed at It was.

Interlevel dielectric consisting of a 200 nm layer of undoped silicon dioxide or conventional L Deposited on individual wafers using PGVD technology. (interlevel dielectric The body avoids contaminating the p-region with phosphorus, or n-type dopants. was not toped. ) This interlevel dielectric is then heated at 9° C. By heating for 0 minutes, it was sealed to a "C" pressure. In addition to this, the wafer is held at 950 degrees. The interlevel dielectric flattens this upper surface by heating for approximately 60 minutes at The source/train region is waved and activated with arsenic and phosphorous implants to was diffused into the wafer to form a .

Use interlevel dielectric or HF to connect source/train region/\ via hole. selectively wet etched to form an ole. (Reactive ion Tetching was intentionally used to avoid the erosion of silicon caused by this etching. There wasn't. ) This pathway hole is achieved using anisotropic reactive ion etching ( It was intended to be a square with sides of 1.25 gm length, but in HF Therefore, the given isotropic etching creates a positive hole with a long side of 2.21L-. They tend to spread out in a square shape.

Processed wafers are divided into three categories (categories E, ■ and M). Ta. Categories I and II are p-type ( Group I) and n-type (Group Category ■ includes two p-type wafers and one p-type wafer. Contains n-type wafers.

A layer of tungsten is applied to the category layer using a two-step process. selectively deposited on the source/train region of the wafer. That is, about l5n- A thick tungsten film or WF6 is first passed across the wafer 1, e.g. , onto a categorical wafer by flowing for about 1 minute at a temperature of 290 degrees Celsius. selectively deposited (via the reaction given in equation (1)). Inside the deposition chamber The thickness of the WF6 was 400 Pa (3) mil), and the partial pressure of WF6 was 0.67 Pa (5 mil). (little) and the partial pressure of argon made up the remainder of the total pressure, approximately 50 An additional layer of tungsten with a thickness of For example, by flowing the water at a temperature of 290 degrees C for about 15 minutes (given in equation (2)), selectively deposited (through a chemical reaction). The total pressure inside the deposition chamber is 186 ．． The partial pressure of WF is 1jPa (10 millitorr). The partial pressure of H2 made up the remainder of this total pressure.

A layer of tungsten approximately 50 rows thick was heated on the wafer for approximately 15 minutes at a temperature of 290 degrees Celsius. Across WF6. Category H by flowing H2 and S iF t. selectively deposited on the source/train region of the wafer. in the deposition chamber The total pressure is 1891 Pa (1,42), and the partial pressure of WF6 is 1.3 Pa (1,42) 0 mTorr), and the partial pressure of S + F4 is 6.7 Pa (20 mTorr). The partial pressure of H2 then made up the remainder of this total pressure.

Processing of category M wafers is similar to category ■ wafer processing and tungsten processing. Platinum silicide (platinum 5i) is deposited on the source/drain regions prior to the formation of the The only difference is that a layer of liside is formed. In other words, the wave of category m It was first washed with a solution of HNO3/H2SO4. next.

A 20nLD thick layer of platinum is sputter deposited on the upper surface of the wafer and A gas containing 90 percent argon and 10 percent oxygen (by volume) It was sintered at 650 degrees Celsius for about 15 minutes in a gas atmosphere. As a result, about 40rv A thick layer of platinum silicide is selected over the exposed upper surfaces of the source and train. was formed. The remaining unreacted platinum was removed using aqua regia. tungsten Prior to fabrication, the wafers were cleaned using a 100:IFII solution.

Following the selective tungsten deposition procedure, all wafers in categories E, ■ and ■ Ha was metallized. In other words, a 1 μm thick AI-1/2% Cu film is sputtered onto various wafers. Then the aluminum on the interlevel dielectric , B( I! /α2 atmosphere and selectively reactive ion etching.

All wafers have contact resistances to the source and train regions of traditional Kelvin. A function of the concentration N of the source/fin 24 surface doping using the (Kelvin) method. It was measured as. In this regard, for example, R, A, Levy (R, A, Levy) ) paper [In-source AI-0,5% Cu metallization for C-OS devices ( In-5source AI-○, 5X Cu Metallization forCMO3Devices)], jar o　　　゛゛ Electro Chemical Society (Journal of the Electroche) mi-cal 5ociety), Vol, 132 pages 159.1985 Please refer. To test the thermal stability of these contact resistances, wafer The individual The contact resistance was measured after the sintering procedure.

The value of the contact resistance measured as a function of N is plotted from Figure 8 to Figure 1O. has been recorded. Figures 8 and 8 show the results achieved with category wafers. As is clear from FIG. 9, the contact resistance to the p source/train region is higher than the value for the n region at equivalent surface doping concentrations. In addition to this, Contact resistance to both the n and p regions is thermally unstable. In other words, sintering Great rise after the procedure.

Figure 1O shows the results achieved with wafers of category ■ and category m. show. As is clear from the figure, the contour to the p region in the wafer of category ■ contact resistance is equal to or lower than the contact resistance to the n-region, and both sets of contacts Both contact resistances are thermally stable. In addition to this, the category C shows a greatly reduced and thermally stable contact resistance to both the n and − regions. vinegar.

Scanning electron, and and transmission electronic microbluffs were taken. These micrographs are Category II The source and train regions in the wafers of It was shown that the area had undergone significantly less vertical and lateral erosion than the corresponding area.

n now nφ FIG.8 FIG.9 Surface doping concentration 1jjN□ (40" Crn-") FIG, 10 Surface doping column hi0 ((O”am-3) country a!lIi inspection report mnffj++1+＾eek+1iee-・PCT/υS 87101230 ANNEX τOTHE rNT3RNATl○NAL 5EARCHR1? O RT ON

Claims (16)

[Claims] 1. In a method for manufacturing a device, a treated or processed material containing a substrate material is forming a metal-containing material on an untreated area of the substrate; The forming step comprises forming at least the first reactive entity into at least a second reactive entity and reacting with the substrate material, the reaction between the first and second entities causing the gold to react with the substrate material; the method further comprises a step to complete the manufacture of the device. between the first reactive entity and the substrate material during the metal forming step. the reaction rate between the first and second reactive entities is substantially reduced. A method characterized in that the amount is lowered. 2. The method according to claim 1, wherein the step of reducing the reaction rate is a first step. the concentration of the products of the reaction between the reactive entity and the substrate material is determined by the concentration of the first and second entities. A method characterized in that the method comprises the step of increasing the degree without increasing it. 3. In the method according to claims 1 and 2, A method characterized in that the substrate material comprises a semiconductor material. 4. The method according to claim 3, wherein the semiconductor material contains silicon. A method characterized by: 5. The method according to any one of claims 1, 2, 3, or 4 There, The semiconductor material includes silicon and the metal includes aluminum. Method. 6. In the method according to any one of claims 1 to 6, At least one of the barriers is tungsten, tantalum, titanium, molybdenum, and A method characterized in that it comprises at least one of rhenium. 7. In the method according to any one of claims 1 to 6, A method characterized in that the first reactive entity comprises WF6. 8. In the method according to any one of claims 1 to 7, A method characterized in that the second reactive entity comprises H2. 9. In the method according to any one of claims 1 to 8, A method characterized in that the product contains SiF4. 10. In a device including at least one n-channel MOSFET, the A MOSFET includes one source/drain, each of the source and drain comprising an n-type semiconductor material; first and second electrical contacts to the source and the drain, respectively; each of the contacts contains metal; the source and drain each have a depth of about 1 μm or less; When the metal penetrates either the source or the drain, or with a corresponding penetration depth shallower than the depth of the drain; A device characterized in that the source and the drain are substantially free from erosion. 11. The device of claim 10, wherein the first voltage to the source the contact resistance of the electrical contact and the second electrical contact to the drain is A device characterized in that it is about 10-6 ohm-cm2 or less. 12. The device according to claim 10, wherein the device comprises the metal and the metal. first and second barriers to interdiffusion of semiconductor materials, the first barrier being the first barrier to the interdiffusion of semiconductor materials; one electrical contact and the source, and the second barrier is located between the second electrical contact and the source. A device, characterized in that it is placed between a tact and the drain. 13. 13. The device of claim 12, wherein the semiconductor material is silicon. , wherein the metal includes aluminum. 14. 14. The device of claim 13, wherein at least one of the barriers is at least one of tungsten, tantalum, titanium, molybdenum, and rhenium. A device comprising: 15. The device according to claim 13, further comprising individual said barriers and said shields. A material region is included between the silicon-containing semiconductor materials, the material region comprising cobalt silicide, cobalt silicide, A compound consisting of titanium silicide, platinum silicide, tantalum silicide, and molybdenum silicide. A device characterized in that it comprises a metal silicide selected from the group. 16. A device according to claim 10, in which at least one p-chip A device comprising a channel MOSFET.