JPS6349932B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an anti-phase signal generation circuit that generates two signals with anti-phase signals based on one input signal.

Conventionally, as this type of negative phase signal generation circuit, as shown in FIG.
FET-Q1) and depletion type (normally-on type) field effect transistor Q2 (hereinafter referred to as FET-Q2 for simplicity) are FET-Q1
A series circuit in which the drain D of the FET-Q2 is connected to the source S of the FET-Q2 is formed by connecting the power line E1 and the power line E2 (grounded).
, FET-Q2 is connected to the power line E1 side, and the gate of FET-Q1 is connected to the input line TO
and the gate of FET-Q2 is connected to FET-Q2
The configuration in which the output line T1 is led out from the gate of FET-Q1, and the other output line T2 is led out from the connection midpoint of FET-Q1 and FET-Q2 is called a direct connection. proposed as a model.

According to this configuration, when the input signal S0, which takes "1" and "0" in binary display, is supplied as "1" to the input line T0, the FET-Q1 turns on, and based on this, the output line An output signal S2 is obtained at T2 as a binary value "0", and an output signal S1 is obtained on an output line T1 as a binary value "1". Furthermore, when the input signal S0 is supplied as "0" to the input line T0, the output signals S1 and S2 are obtained as "0" and "1" on the output lines T1 and T2, respectively.

Therefore, in the case of the configuration of the conventional anti-phase signal generation circuit shown in FIG. 1, it can be said that two signals S1 and S2 of mutually anti-phase can be generated based on one input signal S0. . However, the first
In the case of the configuration shown in the figure, the output signal S2 is the output signal S1
Based on this, it has a configuration obtained by propagating through a series circuit of FET-Q1 and FET-Q2, so there is mutual interaction between output signals S1 and S2 in such a manner that output signal S2 is delayed with respect to output signal S1. Therefore, the output signals S1 and S2 cannot be obtained with a strictly opposite phase relationship.

Also, a negative phase signal generating circuit having the configuration described below with reference to FIG. 2 has been proposed. That is, enhancement type field effect transistors X1 to X4.
(Hereinafter, each will be referred to as FET-X1 to X4 for simplicity)
and a depletion type field effect transistor X as a load with the gate G connected to the source S.
5 and X6, a depletion type field effect transistor X7 as a constant current circuit that connects the gate G to the source, and a level shift diode D.
1 and D2 and resistors R1 and R2 as loads.
and a reference signal source A, and FET-X1
The drains D of and Further FET- through D1 and D2
It is connected to the power supply line E1 through X5 and X6, and the gates G of FET-X1 and
- The gates of X3 and X4 are connected to the midpoint of connection between FET-X1 and resistor R1, and the midpoint of connection between FET-X2 and resistor R2, respectively, and are connected to the midpoint of connection between FET-X1 and resistor R2, and the diode D1
and the connection midpoint of FET-X5, and diode D
Output lines T1 and T2 are led out from the connection midpoints of FET-2 and FET-X6, respectively.

According to the configuration shown in FIG. 2, when the input signal S0 is supplied as "1" to the input line T0, the FET
- X1 and X2 are turned on and off respectively, based on
FET-X3 and X4 turn off and on respectively, thus providing output signals S1 and S2 on output lines T1 and T2.
are obtained when the values are respectively "0" and "1".

Therefore, in the case of the conventional negative phase signal generation circuit shown in FIG. 2, one input signal S0 is used as in the case of FIG.
Two signals S1 and S2 having mutually opposite phases can be obtained based on , in this case, signal S1 is based on signal S0, and a circuit including FET-X1, X2 and X7;
The signal S2 is obtained by propagating through the circuit including FET-X3 and
1, X2 and X6, and a circuit containing FET-X4 and X6.
Circuit containing X3 and X5 and FET-X4 and X6
Since the circuit including the circuit has the same configuration, the two signals S1 and S2 are obtained with strictly opposite phase relationship. However, in the case of the configuration shown in FIG. 2, many components are required, including field effect transistors X1 to X7, diodes D1 and D2, and resistors R1 and R2.
Furthermore, since the FET-X7 is required to constitute a constant current circuit, it has the disadvantage that a relatively high voltage power supply must be connected between the power supply lines E1 and E2.

Therefore, the present invention aims to propose a novel anti-phase signal generating circuit which does not have the drawbacks described above in FIGS. 1 and 2, and this will become clear from the detailed description below.

FIG. 3 shows a first embodiment of an anti-phase signal generation circuit according to the first invention of the present application, which includes a series circuit of an enhancement type field effect transistor M1 and a depletion type field effect transistor M2,
Enhancement type field effect transistor M3
and depression type field effect transistor M4.
A series circuit of an enhancement type field effect transistor M5 and a depletion type field effect transistor M6 is connected to the power supply line E1.
and a power line E2 (grounded), field effect transistors M2, M4, and M6 are connected in parallel to each other with the field effect transistors M2, M4, and M6 on the power line E1 side. Below, the field effect transistors M1 to M6 are FET-M for simplicity.
They are called 1 to M6.

In this case, it is assumed that the drains D of FET-M1, M3 and M5 are connected to the sources of FET-M2, M4 and M6, respectively.

Therefore, the gate G of FET-M1, M3 and M6
is connected to the input line T0, the gate G of FET-M2 is connected to the source S of FET-M2, and
The gates G of FET-M4 and M5 are connected to the connection midpoint of FET-M1 and M2, and furthermore, FET-M
3 and M4 connection midpoint and FET-M5 and M6
Output lines T1 and T2 are led out from the connection midpoints, respectively.

The above is the configuration of the first embodiment of the first invention of the present application. According to this configuration, two lines are connected to the input line T0.
Input signal S0 that takes "1" and "0" in the value display
is supplied with "1", FET-M1 turns on and "0" is applied to the connection midpoint of FET-M1 and M2.
The output of ``0'' turns off FET-M4, while the output of ``0'' does not turn on FET-M5, so it remains off. Also, since the input signal S0 is supplied as "1", FET-M3 is turned on, and further
FET-M6 remains on, so the output signals S1 and S2 are "0" on the output lines T1 and T2, respectively.
and "1". Also, when input signal S0 is supplied, FET-
M1 remains off, thus FET-M1 and M2
An output of "1" is obtained at the midpoint of the connection, and the FET-M5 is turned on by the output of "1".
On the other hand, since the input signal S0 is supplied as "0", FET-M3 is not turned on and therefore remains off, and FET-M6 is turned off, and FET-M3 is not turned on and therefore remains off.
M4 remains on, so that output signals S1 and S2 are obtained as "1" and "0" on output lines T1 and T2, respectively.

Therefore, the first aspect of the first invention of the present application shown in FIG.
In the case of the configuration of the embodiment, two signals S1 and S2 having mutually opposite phases can be generated based on one input signal S0. In this case, signal S1 is based on signal S0, and FET-M1 and M2
and a circuit including FET-M3 and M4, and the signal S2 is obtained by propagating the circuit including FET-M1 and M2 and the circuit including FET-M3 based on the signal S0.
In this case, since the circuit including FET-M3 and M4 and the circuit including FET-M5 and M6 have the same configuration, the two signals S1 and S
2 is obtained in a strictly antiphase relationship.

This shows that when the phase difference between signals S1 and S2 is measured with respect to the gate length of FET-M1 to M6, as shown in the curve in Figure 4, even when the gate length becomes large, the phase difference is almost constant. This became clear from what was obtained with Zero. Incidentally, in the case of the conventional configuration shown in FIG. 1, when the phase difference between signals S1 and S2 with respect to the gate length of FET-Q1 was measured,
As shown by the curve in the figure, the larger the gate length, the larger the phase difference obtained.

Further, the embodiment of the present invention shown in FIG. 3 has a great feature in that the above-mentioned features can be obtained with a simple configuration using only six FETs M1 to M6. Furthermore, a series circuit of FET-M1 and M2, a series circuit of FET-M3 and M4,
The series circuit of FET-M5 and M6 is the power line E1
Since it has a configuration in which it is directly connected between the power lines E1 and E2, it has great features such as not requiring a high voltage power source to be connected between the power lines E1 and E2.

Next, a second embodiment of the first invention of the present application will be described with reference to FIG. 5. Parts corresponding to those in FIG.
In the configuration described above in FIG. 3, the manner in which the depletion type field effect transistors M7 and M8 (hereinafter referred to as FET-M7 and M8, respectively) connect the drain D of the former to the source S of the latter will be described below. are connected in series, and the series circuit is connected between the power supply lines E1 and E2, and the FET-M
In the case of Fig. 3, connect the input line T to the connection midpoint of 7 and M8.
It has the same configuration as the case in Fig. 3, except that 0 is connected as the output line of the circuit including FET-M7 and M8, and the input line S0' is further derived from the gate G of FET-M7. .

The above is the configuration of the second embodiment of the second invention of the present application. According to this configuration, it has the same configuration as the case of FIG. 3 except for the matters mentioned above, and If the same input signal S0 as in the case of FIG. 3 is supplied to the input line T0' as "1" and "0", respectively, "0" and "0" are respectively supplied to the connection midpoint of FET-M7 and M8. Since it is clear that an output of "1" is obtained, the input signal S0 is applied to the output lines T1 and T2.
When is "1", output signals S1 and S2 are obtained as "1" and "0", respectively, and when input signal S0 is "0", output signals S1 and S2 are obtained as "0", respectively.
and "1".

Therefore, also in the case of the second embodiment of the present invention, two signals S0 having mutually opposite phases are generated based on one input signal S0.
1 and S2.
In this case as well, as in the case of Fig. 3, the signals S1 and S2 can be obtained with a strictly antiphase relationship with a simple configuration, and a high voltage power source is not required between the power lines E1 and E2. It has characteristics. In the case of Fig. 3, the input signal S0 has approximately 1/1/1 of its voltage amplitude.
However, in the case of this example shown in Fig. 5,
Since it has a circuit including FET-M7 and M8,
It also has the feature that there is no need to superimpose such a DC bias on the input signal S0.

Next, an embodiment of the second invention of the present application will be described with reference to FIG. 6. Parts corresponding to those in FIG. In the configuration, the FET-M1 and M3
The configuration is similar to that of the case shown in FIG. 3, except that the enhancement type is replaced with a depletion type.

The above is the configuration of the embodiment of the second invention of the present application, but according to this configuration, it is the same as the case of FIG. 3 except for the matters mentioned above, so detailed explanation thereof will be omitted. However, the same effect as in the case of FIG. 3 can be obtained. However, in this example, the input signal S
Since the FETs M1 and M3 to which 0 is supplied are both depletion type, there is no need to superimpose a DC bias on the input signal S0, as in the case of FIG.

[Brief explanation of drawings]

Figures 1 and 2 are connection diagrams showing conventional circuits;
3 is a connection diagram showing an embodiment of the first invention of the present application, FIG. 4 is a curve diagram for explaining the same, FIG. 5 is a connection diagram showing a second embodiment of the first invention of the present application, FIG. 6 is a connection diagram showing an embodiment of the second invention of the present application.

Claims (1)

[Scope of Claims] 1. A first series circuit including a first enhancement type field effect transistor and a depletion type second field effect transistor, a third enhancement type field effect transistor and a depletion type fourth field effect transistor. a second series circuit with a fifth field effect transistor of an enhancement type and a sixth field effect transistor of a depletion type;
and a second power supply line, the second, fourth and sixth field effect transistors are connected in parallel with each other with the first power supply line side, and the first, third and sixth field effect transistors are The gate is connected to the input line,
The gate of the second field effect transistor is connected to the source or drain of the second field effect transistor connected to the side connected to the first field effect transistor, and the gate of the second field effect transistor is connected to the source or drain of the second field effect transistor connected to the first field effect transistor. a gate connected to a connection midpoint of the first and second field effect transistors, and from a connection midpoint of the third and fourth field effect transistors and a connection midpoint of the fifth and sixth field effect transistors; An anti-phase signal generation circuit characterized in that first and second output lines are respectively derived. 2. A first series circuit of depletion type first and second field effect transistors, a second series circuit of depletion type third and fourth field effect transistors, and an enhancement type fifth field effect transistor. and a sixth field effect transistor of the depletion type.
between the first and second power supply lines;
field effect transistors are connected in parallel to each other with the first power supply line side connected, the gates of the first, third and sixth field effect transistors are connected to the input line, and the gate of the second field effect transistor is connected to the input line. is connected to the source or drain of the second field effect transistor connected to the side connected to the first field effect transistor, and the gates of the fourth and fifth field effect transistors are connected to the first and second field effect transistors. first and second output lines connected to the connection midpoint of the field effect transistors, respectively from the connection midpoint of the third and fourth field effect transistors and the connection midpoint of the fifth and sixth field effect transistors; An anti-phase signal generation circuit characterized in that the following is derived.