JPS58188936A - High-speed frequency dividing circuit - Google Patents

Abstract

PURPOSE:To perform high-speed transmission, by driving a master and a slave frequency divider by a push-pull inverter capable of generating two driving signals which are out of phase with each other while their phase difference is almost eliminated. CONSTITUTION:A signal S1 appearing at the output side of a transistor TR29a is delayed in phase behind a signal S2 appearing at the output side of a TR28a by as much as it passes through the TR29a. Those signals S1 and S2 are supplied to TRs 31b and 32a, and 32b and 31a of the push-pull inverter circuit 3 to obtain output signals S2 and S4 at the output sides of the TRs 31a and 32a. Then, this circuit 3 outputs signals phi and phi' which are in phase with each other. Those signals phi and phi' are frequency-divided by 2 through the frequency dividing circuit 4 consisting of latch circuits 41 and 43, and a sampling circuit 42 and then supplied to the next stage through a sense amplifier 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed frequency divider circuit suitable for use, for example, in a data transmission system.

In a mask/slave branch divider generally used in a data transmission system, the mask side and the slave side are controlled by two drive signals φ and i having mutually opposite phases. However, in the case of the conventional circuit, a phase error occurs between the first drive signal φ and the second drive signal 1 as shown in FIG. The button to end the process is pressed for a predetermined time, for example, as shown in FIG. was there.

In view of this, the present invention makes the phase shift between the first drive signal φ and the second drive signal ¥ zero, and eliminates the wasted time that occurs in conventional circuits, making it possible to increase the speed. This provides a high-speed frequency divider circuit.

Hereinafter, one embodiment of the present invention will be described in detail based on FIG. 2.

In Figure 2, (1) is an input signal source, (2) is an inverter circuit, and (3) is a Bushdel inverter circuit, which are driven by the inverter circuit (2) and Bushdel inverter circuit (3). configuring the amplifier.

Further, (4) is a so-called master-slave divider, for example, a pot divider, and (5) is a sense amplifier.

One end of the input signal source (1) is connected to the ground terminal GND,
The other end is connected to the inverter circuit (2) via the capacitor 0υ.
is connected to the e-) terminal of the field effect transistor (21a). The source terminal of the transistor (21a) is connected to the ground terminal GNDK, and the drain terminal is connected to the positive power supply terminal VDD via the source terminal-drain terminal of the field effect transistor (21b), and the transistor (21b)
The dart and source terminals of are interconnected. These transistors (21 and (21b)) constitute a so-called innovator at the first stage.

Also, the connection point between the drain terminal of the transistor (21a) and the source terminal of the transistor (21b) is connected to the dirt terminal of a field effect transistor (22m) constituting the next stage inverter, and the source terminal of this transistor (22a) is grounded. It is connected to the terminal GND, the drain terminal is connected to the positive power supply terminal VDD via the source terminal-drain terminal of the field effect transistor (22b), and the c-)m terminal and the source terminal of the transistor (22b) are interconnected. Ru. The connection point between the drain terminal of the transistor (22m) and the source terminal of the transistor (22b) is connected to the f-) terminal of the field effect transistor (23m) that constitutes the next stage inverter, and the source terminal of the transistor (23a) is It is connected to the ground terminal GND, the drain terminal is connected to the positive power supply terminal VDD K via the source terminal-drain terminal of the field effect transistor (23b), and the transistor (
The dart terminal and source terminal of 23b) are interconnected.

Similarly, the field effect transistor (24m) and (24b)
), field effect transistors (25m) and (25b),
Field effect transistors (26m) and (26b), field effect transistors (27m) and (27b), field effect transistors (28m) and (28b), and field effect transistors (29m) and (29b) constitute an inverter, respectively. , cascaded. Furthermore, transistors (21m) to (29m)
The transistors (21b) to (29b) act as load elements of the inverter, and are of the N-channel depletion type, for example. used.

And the connection point between the drain terminal of the transistor (29 Hatake) and the source terminal of the transistor (29b)! Field effect transistor (31
m) is connected to the r-t terminal of the transistor (2Sa).
A connection point between the drain terminal of the transistor (28b) and the source terminal of the transistor (28b) is connected to the dirt terminal of the field effect transistor (31b). The source terminal of the transistor (31a) is connected to the ground terminal GND, and the drain terminal is connected to the power supply terminal VDDK via the source i-drain terminal of the transistor (31b). Also, a transistor (31b
) is connected to the f-) terminal of the field effect transistor (32m), and the dart terminal of the transistor xp (31a) is connected to the e-) terminal of the field effect transistor (32b).
Connected to the terminal. The source terminal of the transistor (32a) is connected to the ground terminal GNDK, and the drain terminal is connected to the power supply terminal VDD via the source terminal-drain terminal of the transistor (32b). These transistors (31m) (31b) and (32m) (32b)
Nyoshi! It constitutes the first Gutshudel inverter of the Tsushugur inverter circuit (3). Also, transistor (
The connection point between the drain terminal of the transistor (32m) and the source terminal of the transistor (32b) is the field effect transistor (33m).
The connection point between the drain terminal of the transistor (31Jl) and the source terminal of the transistor (31b) is connected to the f-) terminal of the field effect transistor (33b). The source terminal of the transistor (33m) is connected to the ground terminal GND, and the drain terminal is connected to the power supply terminal VDD via the source terminal-drain terminal of the transistor (33b). Furthermore, a transistor (
The ff-) terminal of 33b) is a field effect transistor (34
connected to the dart terminal of a), and the transistor (33a)
The y-to terminal of the field effect transistor (34b) is the r- terminal of the field effect transistor (34b).
) terminal. The source terminal of the transistor (34a) is connected to the ground terminal GND, and the drain terminal is connected to the power supply terminal VDD via the source terminal-drain terminal of the transistor (34b). These transistors (33a) (33b) and transistor (34a)
) (34b) Yosigusheguru inverter circuit (3)
This constitutes the second Bushdel inverter. For example, N-channel enhancement type transistors are used as the transistors (31m) to (3ta), and N-channel depletion type transistors are used as the transistors (31b) to (34b).

Also, the output side of the Gutshugur inverter circuit (3), for example the drain side of the transistor (34a), and the input side of the inverter circuit (2), for example the transistor (21m+)
By connecting a feedback resistor α2 between the f-) terminal of
The operating points of the inverter circuit (2) and the inverter circuit (3) are stabilized.

The divider (4) consists of a latch circuit (40) on the mask side, a sampling circuit (44), and a latch circuit (44) on the slave side. Field effect transistor (41a
) (41b) and field effect transistor (41e) (
A pair of field effect transistors (41d) and f-) for
41e) (41f) are provided. The transistors (41C), (41a), and (41e) are connected in series between the power terminal VDD and the ground terminal GND, and similarly, the transistors (41d, 41b, and 41f) are connected to the power terminal Vpi.
, and the ground terminal GND. The e-) terminals of the transistors (41m) (41d) are interconnected, and the f- terminals of the transistors (41b) (41c) are interconnected.
) terminals are interconnected. Also transistor (41c)
(41d) each? -) and source terminals are interconnected, while each f of the transistors (41e) and (41f)
-) terminals are connected to one output side of the circuit (3), such as a transistor (33a
) is connected to the connection point between the drain terminal of the transistor (33b) and the source terminal of the transistor (33b). Furthermore, transistor (41m)
(41b) (41e) As (41f), for example, an N-channel enhancement type is used,
On the other hand, as the transistors (41e) (41d), for example, N-channel depletion type transistors are used.

The sampling circuit (6) consists of a pair of field effect transistors (42m) (42b) and a dirt field effect transistor (40c), and a transistor (421).
Each drain terminal of (42b) is connected to a transistor (41
a) Connected to each drain terminal of (41b), and each source terminal of transistors (42a) and (42b) connected in common, and then connected to ground terminal GND via the drain terminal and source terminal of transistor (42c). . The f- upper terminal of the transistor (42c) is connected to the other output side of the Bushgur inverter circuit (3), for example, the transistor (42c).
It is connected to the connection point between the drain terminal of the transistor (34m+) and the source terminal of the transistor (34b). In addition, transistor (4
2a) (42b) (42c), for example, an N-channel enhancement type is used.

In addition, the latch circuit on the slave side (4) is a pair of field effect transistors (43
m) (43b) and field effect transistor (43c)
(43d)? -) a pair of field effect transistors for (
43e) (43f). And the field effect transistor (43cX43a) (43e) is the power supply terminal VD
Similarly, transistors (43d) (43b) (43f) are connected in series between D and the ground terminal GND.
Il) II child VDD is connected in series between Ijlkllll and GND. And transistors (43a) and (4
The f-) terminals of 3d) are interconnected, and the dart terminals of transistors (43b) and (43c) are interconnected. Also, the respective f-) terminals and source terminals of the transistors (43C) and (43d) are connected to each other, while the respective dart terminals of the transistors (43e) and (43f) are connected in common and are connected to each other in a similar manner to the sampling circuit (6). The other output side of the group inverter circuit (3), that is, the transistor (
It is connected to the connection point between the drain terminal of the transistor (34m) and the source terminal of the transistor (34b).

Further, each drain terminal of the transistor (43si) (43b) is connected to each r-) terminal of the transistor (42a) (42b) of the sampling circuit 143 on the mask side, respectively.

Transistor (43m) (43b) (43e)
For example, an N-channel enhancement type transistor is used as the transistor (43f), while the transistor (43c
) (43d), for example, an N-channel depression type is used.

Similar to sampling circuit (6), sampling circuit m includes a pair of field effect transistors (44g) (44b) and r-
Each drain terminal of the transistor (44a) (44b) is a connection point between the drain terminal of the husband transistor (43 Hatake) and the f-) terminal of the transistor (42g), and a field effect transistor (44c) for (43b) and the dirt terminal of the transistor (42b), respectively.
The respective source terminals of 4a) (44b) are commonly connected and connected to the ground terminal GNDK via the drain terminal-source terminal of the transistor (44c). Also, transistor (
Each dart terminal of 44a) (44b) is connected to each drain terminal of transistor (42b) (42a) and also connected to each drain terminal of transistor (41b) (41a), and the dart terminal of transistor (44c) is connected to each drain terminal of transistor (42b) (42a). The latch circuit (similar to 40! Connected to one output side of the shuffle inverter circuit (3), that is, the connection point between the drain terminal of the transistor (33a) and the source terminal of the transistor (33b).
4b) As (44c), for example, an N-channel enhancement type is used.

The sense amplifier (5) may be, for example, a pair of series-connected field effect transistors arranged in parallel between the power supplies.
(51a) and (51b) - (52g) and (52b)
, (53a) and (53b), and the transistor (
Each source terminal of 51a) (52a) (53a) is connected to the ground terminal GND, and each drain terminal is connected to the power supply terminal VDD via each source terminal-drain terminal of the transistor (51b) (52b) (53b), respectively. be done.

The terminal of the transistor (51a) is
(43b) connected to the node terminal,
The dirt terminal of the transistor (51b) is connected to the transistor (51b).
43b). Also, the connection point between the drain terminal of the transistor (51a) and the source terminal of the transistor (51b) is the f-) of the transistor (52a).
The dirt terminal and source terminal of the transistor (52b) are interconnected. Also transistor (5
The connection point between the drain terminal of 2a) and the source terminal of the transistor (52b) is connected to the e-) terminal of the transistor (53m), the f-) terminal and the drain terminal of the transistor (53b) are interconnected, and the transistor (53a)
An output terminal to the next stage is taken out from the connection point between the drain terminal of the transistor (53b) and the source terminal of the transistor (53b). In addition,
Here, 4 transistors (51b) This transistor (51b) also supplies the output signal of the previous stage.
51b) in a source follower manner to obtain an output signal approximately similar to the input signal at its output side. This makes it possible to obtain a clean waveform with a duty of -50%.

Next, the operation of the circuit shown in FIG. 2 will be explained. Now the input signal source (
1) The input signal at the top is sequentially inverted by each inverter of the inverter circuit (2) and transmitted from the previous stage to the top stage. Now considering the signal relationship between the two inverters in the latter stage of the inverter circuit (2), the signal s1 obtained from the output NK of the transistor (2Sa) and the signal 82 (81) obtained at the output side of the transistor (29a) are the latter. The phase is different from that of the signal S1 by the amount that passes through the transistor (29a). Therefore, these signals 81 e 82 are respectively connected to the transistors (3) of the first Gutschdel inverter.
1b) (32a) and transistor (32b) (31
a), transistors (31m) and (32a
), an output signal 83 and an output signal S4 are taken out, respectively. Here, these output signals 83, S, are respectively input signals S1. Note that S2 is produced in the combined signal. That is, for example, signal S3 is signal S
The signal S1, which is slightly ahead of 2 in phase, is transmitted by the transistor (3
The signal S2 which is supplied to the date terminal of 1b) and which is slightly slower in phase than the signal Sl is connected to the transistor (31m).
- The blade output signal s4 is generated by supplying the signal sl to a transistor (32m
) and the signal S2 is supplied to the f-) terminal of the transistor (32b). Additional output signal S3. S4 is created such that the phase errors of the signals Sl and s2 cancel each other out, and therefore the phase error between the output signals S3 and 84 is substantially close to zero. Furthermore, these signals S3. The transistors x l of the second Butschgru inverter with S4 as input signals, respectively.
Transistors (33a) and (34a) by supplying (33b) (34a) and (33a) (34b)
Output signals S5 and s6 are taken out from the output side, respectively,
The phase errors of these output signals S5 and S86 are also canceled out for the above-mentioned reason, and the phase errors are even smaller than in the case of the signals s3e and s. Therefore, as shown in FIG. 1 BK, the driving signals φ and 7 without any phase error are taken out from the output side of the Bushgur inverter circuit (3). Become. At this time, the control operation time for one cycle of both signals is T2 (<TI) as shown in FIG. 1B, and it can be seen that approximately IA of wasted time is removed from this K, and high speed can be achieved.

Next, the operation of the branching device (4) will be explained. Latch circuit 41)
and (43 are respectively in the hold state and hold release state when the drive signal φ is at a high level, that is, when the drive signal ¥ is at a low level; - when the level of the blade drive signal is reversed, each latch circuit (41) operates so that the hold release state and the latch circuit (43) enter the hold state.Now,
When the drive signals φ and i become low level and high level, respectively, the latch circuit (4) is released from its hold state, while the latch circuit (1) enters the hold state.Then, the sampling circuit transistor (42c) becomes high level. The drive signal 1 is applied to the transistors (42a) and (
42b) are turned on by the output Qt a Q2 of the latch circuit 143 in the hold state, and these transistors (
42g) (42b) is the transistor of latch circuit I (
41c) and (41d) work as husband and wife inverters. Therefore, the signal Q2 is on the output side of the transistor (42a).
is inverted, a nine signal Q1 is obtained, and the transistor (4
2b), a signal Qz which is an inversion of the signal Q2 is obtained. That is, at this time, outputs obtained by inverting the outputs of the latch circuit (41) are obtained on the output side of the latch circuit (41).

When the drive signals φ and 'i change from high level to low level, the latch circuit (41) changes from the sampling state to the holding state. That is, the latch circuit will hold the state before switching.

The hold state of this latch circuit (4D) is then sent to the latch circuit (41). That is, the inverted signal of the output signal Q1-Ql is sent to the latch circuit AI.

In this way, the latch circuits (41) and +43 inherit data that is out of phase with each other, and therefore, when looking at one latch circuit from the other, one latch circuit has the same data as the other. The opposite of the first data will be sent from the latch circuit. In other words, the transmission signal is frequency-divided by 9 times.

The divided output signal whose frequency has been divided by the frequency divider (4) in this manner is supplied to the next stage via the sense amplifier (5).

Note that the transistors for the latch circuit 141) 143 and the sampling circuit (f- of 43 (44)) are a pair of transistors for the former and a single transistor for the latter; It is possible to use any combination of transistors, a pair of transistors for the latter, a pair of transistors for both the former and the latter, or a single transistor for the former and the latter. however,
When considering speedup, in a sampling circuit, a single transistor has a faster sampling time, whereas in a latch circuit, the time required to enter the hold state and release the hold becomes a problem if the speed is increased, so it is better to use a pair of transistors. The latch release time becomes faster. Therefore, the configuration of this embodiment can be said to be the most preferable arrangement for increasing speed.

As described above, according to the present invention, a drive signal can be generated based on the phase error! Since the master/slave splitter is driven by the pull imperper, it is possible to eliminate the wasted time due to the phase error that conventionally occurs between the two drive signals, thereby enabling high-speed transmission.

Also, since the DC component of the output of the Zotsupu inverter is fed back to the input side of the inverter, the inverter and! A phenomenon in which the operating point of the drive amplifier is stabilized, and the unbalance between high and low levels that occurs in conventional circuits is amplified and becomes stuck on one level side. will also be resolved.

In the above embodiment, IA is used as a mask slave divider.
Although the description has been made for the case of a frequency divider, the present invention can be similarly applied to other frequency dividers such as a 1/4 frequency divider and a 1/6 frequency divider by increasing the number of latch circuits and sampling circuits.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an example in which the present invention is compared with the operation of a conventional circuit. (1) is the input signal source, (2) is the interface circuit, (3
)teeth! Tschuguru inverter circuit, +4+u-i frequency divider (master-slave frequency divider L (5) is a sense amplifier. Same as Hidemori Matsukuma)

Claims (1)

[Claims] 1. At least one inverter and at least one!
The above! A high-speed frequency divider circuit whose special purpose is to drive the above-mentioned mask/slave divider with the output of the Tsushiegle inverter. 2. Feed back the DC component of the output of the Butsuguru Imperator to the input side of the Innocutor to the above-mentioned inverter and! 2. The high-speed branching circuit according to claim 1, wherein K is set to stabilize the operating point of the tush-pull imperter.