JPS6349861A - Method for processing battery fault - Google Patents

Method for processing battery fault

Info

Publication number
JPS6349861A
JPS6349861A JP61193417A JP19341786A JPS6349861A JP S6349861 A JPS6349861 A JP S6349861A JP 61193417 A JP61193417 A JP 61193417A JP 19341786 A JP19341786 A JP 19341786A JP S6349861 A JPS6349861 A JP S6349861A
Authority
JP
Japan
Prior art keywords
memory
battery
fixed data
rom
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61193417A
Other languages
Japanese (ja)
Other versions
JPH0373015B2 (en
Inventor
Mikio Uehara
幹生 上原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61193417A priority Critical patent/JPS6349861A/en
Publication of JPS6349861A publication Critical patent/JPS6349861A/en
Publication of JPH0373015B2 publication Critical patent/JPH0373015B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W88/00Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/08Access point devices
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W24/00Supervisory, monitoring or testing arrangements

Abstract

PURPOSE:To enable information of battery fault by writing previously the fixed data recorded to a ROM to a memory and comparing this fixed data with that read out of the ROM in an application mode of a power supply, and clearing a timepiece data, if the result is inconsistency. CONSTITUTION:When a power supply 7 is switched off, a switch 8 is connected to a battery 9 and the power of the battery 9 is supplied to a memory 3 as well as a timepiece 4. When the power supply 7 is applied, the switch 8 is connected to the power supply 7 and a current is supplied to the memory 3 and the timepiece 4. A processor 1 works after reading a program out of a ROM 2 and compares the fixed data written to the memory 3 with that read out of the ROM 2. When no coincidence is obtained between both data, the processor 1 clears the timepiece 4 and displays an indication at a display part 5 to set a time point, etc. (A battery fault can also be displayed.)

Description

【発明の詳細な説明】 〔概要〕 電池で揮発性メモリと時計のバックアップを行い、電源
切断時にもメモリに格納したデータを保存する情報処理
装置において、ROMに記録した固定データをメモリに
書込んでおき、電源投入時に比較することで、不一致と
なった時、電池障害と判定して、時計データをクリアす
ることで、オペレータに電池障害を通知する。
[Detailed Description of the Invention] [Summary] In an information processing device that backs up volatile memory and a clock using a battery and saves data stored in the memory even when the power is turned off, fixed data recorded in a ROM is written to the memory. When the power is turned on and compared, it is determined that there is a battery failure, and the clock data is cleared to notify the operator of the battery failure.

〔産業上の利用分野〕[Industrial application field]

本発明は電池を用いて揮発性メモリや時計をバックアッ
プする情報処理装置に係り、特に電池でバックアップ中
に発生した電池障害により、メモリに記憶中のデータが
破壊されていた場合の電池障害に対する処理方法に関す
る。
The present invention relates to an information processing device that backs up a volatile memory or a clock using a battery, and in particular, processing for a battery failure when data stored in the memory is destroyed due to a battery failure that occurs during backup using a battery. Regarding the method.

情報処理装置において、揮発性メモリの内容を保存した
り、日時データを保持するため、情報処理装置の電源を
切断した時、電池でバンクアップすることは公知である
。ところで、この電池が消耗して電圧が低下し、メモリ
の内容が破壊されることがある。
2. Description of the Related Art In an information processing device, it is known that a battery is used to power up the volatile memory in order to save the contents of the volatile memory and hold date and time data when the information processing device is powered off. By the way, this battery may become exhausted and the voltage may drop, causing the contents of the memory to be destroyed.

従って、メモリの内容が破壊されているか否かを調べる
必要があるが、例えばROMに書込まれている固定デー
タをメモリに書込んで置き、情報処理装置の電源を投入
する度に、ROMから読出した固定データとメモリに書
込んである固定データとを比較することで、電池障害を
検出することが出来る。
Therefore, it is necessary to check whether the contents of the memory have been destroyed or not. For example, if fixed data written in the ROM is written to the memory, and every time the information processing device is turned on, the data will be deleted from the ROM. A battery failure can be detected by comparing the read fixed data with the fixed data written in the memory.

このようにして、電池障害を検出した時、この障害を情
報処理装置のプロセッサに通知して、その後の処理を円
滑に実行し得るようにすることが必要である。
In this way, when a battery failure is detected, it is necessary to notify the processor of the information processing device of the failure so that subsequent processing can be executed smoothly.

〔従来の技術〕[Conventional technology]

従来、電池でメモリや時計のバックアップを行っている
情報処理装置で、メモリに固定データを記録し、電源投
入毎に固定データの比較を行って電池障害を検出してい
るものが無いため、メモリ内容が破壊されていても、情
報処理装置のプロセッサには通知されていない。
Conventionally, information processing devices that use batteries to back up memory and clocks record fixed data in memory and compare fixed data every time the power is turned on to detect battery failures. Even if the contents are destroyed, the processor of the information processing device is not notified.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記の如く、電池でバックアップされているメモリの内
容や時計の日時データが破壊されていても、情報処理装
置のプロセッサには通知されないため、オペレータが電
源投入時に見逃すと、誤ったデータを処理したり、誤っ
た日時が記録されるという問題がある。
As mentioned above, even if the contents of the battery-backed memory or the date and time data on the clock are destroyed, the processor of the information processing equipment is not notified, so if the operator misses it when turning on the power, the data may be processed incorrectly. There is a problem that the wrong date and time are recorded.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明の一実施例を示す回路のブロック図であ
る。
FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention.

1は装置全体を制御するプロセッサ、2はプロセッサl
の動作を指示するプログラムと固定データが格納された
ROM、3は連発性のメモリ、4は時計、5は表示部、
6はオペレータが命令等を入力するキーボード、7は電
源、8はスイッチ、9は電池である。
1 is a processor that controls the entire device, 2 is a processor l
3 is a continuous memory, 4 is a clock, 5 is a display section,
6 is a keyboard through which an operator inputs commands, etc.; 7 is a power source; 8 is a switch; and 9 is a battery.

プロセッサ1は電源7に電源が投入された時、ROM2
から固定データを読出し、メモリ3に書込んである固定
データと比較し、−敗しなければメモリ3と時計4をク
リアする構成とする。
When the power supply 7 is turned on, the processor 1 stores the ROM 2
Fixed data is read from the memory 3, compared with the fixed data written in the memory 3, and if there is no failure, the memory 3 and the clock 4 are cleared.

〔作用〕[Effect]

上記構成とすることにより、プロセッサ1は電源が投入
される度にメモリ3の固定データが破壊されているか否
かで電池9の障害を判定し、メモリ3の固定データが破
壊されている場合、メモリ3と時計4をクリアするため
、プロセッサ1の立ち上がり時に、時計4の日時データ
を調べた時、日時データが零となっていることから、時
計の設定指示を表示すること等により、電池障害をオペ
レータに通知することが出来る。
With the above configuration, the processor 1 determines whether the battery 9 has failed each time the power is turned on, depending on whether the fixed data in the memory 3 is destroyed, and if the fixed data in the memory 3 is destroyed, In order to clear the memory 3 and clock 4, when the processor 1 starts up, the date and time data of the clock 4 is checked. Since the date and time data is zero, the battery failure is detected by displaying clock setting instructions, etc. The operator can be notified.

〔実施例〕〔Example〕

第2図は第1図の動作を説明するフローチャートである
FIG. 2 is a flowchart explaining the operation of FIG. 1.

第1図において、電源7の電源が切断されると、スイッ
チ8は点線で示す如く電池9側に接続され、電池9の電
流がメモリ3と時計4に供給される。
In FIG. 1, when the power source 7 is turned off, the switch 8 is connected to the battery 9 side as shown by the dotted line, and the current from the battery 9 is supplied to the memory 3 and the clock 4.

電源7に電源が投入されると、スイッチ8は実線で示す
如く接続され、電源7から電流がメモリ3と時計4に供
給される。スイッチ8は無瞬断スイッチであることは勿
論である。
When the power source 7 is turned on, the switch 8 is connected as shown by the solid line, and current is supplied from the power source 7 to the memory 3 and the clock 4. Of course, the switch 8 is a non-stop switch.

プロセッサ1はROM2からプログラムを読出して動作
し、第2図に示す如く、メモリ3に書込まれている固定
データと、ROM2から読出した固定データとを比較す
る。ここで、比較結果が一致すれば時計4がクリアされ
ているか否かを調べ、クリアされていなければ、通常の
処理に移行し、キーボード6から入るオペレータの指示
により動作する。
The processor 1 operates by reading a program from the ROM 2, and compares the fixed data written in the memory 3 with the fixed data read from the ROM 2, as shown in FIG. Here, if the comparison results match, it is checked whether the clock 4 has been cleared or not, and if it has not been cleared, the routine shifts to normal processing and operates according to the operator's instructions entered from the keyboard 6.

メモリ3の固定データとROM2の固定データとが一致
しない時、プロセッサ1はメモリ3をクリアした後、R
OM2から固定データを読出し、メモリ3に書込む。そ
して、時計4のクリアを行う。次いで時計4がクリアさ
れているか否か調べ、クリアされていると例えば時刻設
定の指示を表示部5に表示する。(電池障害と表示して
も良いことは勿論である) オペレータは時計がクリアされていることから、電源切
断中にメモリ内容が破壊されたことを知り、時計の時刻
を設定を行う。プロセッサ1は通常処理に移行する。
When the fixed data in memory 3 and the fixed data in ROM2 do not match, processor 1 clears memory 3 and then
Fixed data is read from OM2 and written to memory 3. Then, clock 4 is cleared. Next, it is checked whether the clock 4 has been cleared, and if it has been cleared, an instruction to set the time, for example, is displayed on the display section 5. (Of course, it may be displayed as a battery failure.) Since the clock has been cleared, the operator knows that the memory contents were destroyed while the power was turned off, and sets the time on the clock. Processor 1 shifts to normal processing.

〔発明の効果〕〔Effect of the invention〕

以上説明した如(、本発明は電池でバックアップしてい
るメモリや時計が、電池障害で内容が破壊されている時
、メモリと時計をクリアするため、電池障害をオペレー
タに通知することが出来ると共に、メモリクリアを人手
で行う手間が省ける効果がある。
As explained above, the present invention clears the memory and clock when the contents of the battery-backed memory and clock are destroyed due to a battery failure, and can notify the operator of the battery failure. This has the effect of saving the effort of manually clearing the memory.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路のブロック図、 第2図は第1図の動作を説明するフローチャートである
。 図において、 1はプロセッサ、  2はROM。 3はメモリ、     4は時計、 5は表示部、     6はキーボード、7は電源、 
     8はスイッチ、9は電池である。 二 ・杢発日月の一実方琶・沙・]苔力でJ謂T該jイリフ
′口・ソフ図第1図 1も1図のすカイY左宕死日月Iろフr)?v−ト膚5
2 図
FIG. 1 is a block diagram of a circuit showing one embodiment of the present invention, and FIG. 2 is a flowchart explaining the operation of FIG. 1. In the figure, 1 is a processor and 2 is a ROM. 3 is memory, 4 is clock, 5 is display, 6 is keyboard, 7 is power supply,
8 is a switch, and 9 is a battery. 2. 杢发日月Ichihowa・sa・] Moss power and J 謂T 類j Irif'口・SOF fig. ? v-to skin 5
2 figure

Claims (1)

【特許請求の範囲】 電池(9)を用いて揮発性メモリ(3)及び時計(4)
のバックアップを行う情報処理装置において、 不揮発性メモリ(2)から該揮発性メモリ(3)に固定
データを書込んでおき、情報処理装置の電源を投入した
時に、該不揮発メモリ(2)から読出した固定データと
該揮発性メモリ(3)に書込んだ固定データを比較し、
不一致となった場合、該揮発性メモリ(3)及び時計(
4)のデータをクリアすることを特徴とする電池障害に
対する処理方法。
[Claims] Volatile memory (3) and clock (4) using a battery (9)
In an information processing device that performs backup, fixed data is written from a nonvolatile memory (2) to the volatile memory (3), and when the information processing device is powered on, it is read from the nonvolatile memory (2). Compare the fixed data written in the volatile memory (3) with the fixed data written in the volatile memory (3),
If there is a mismatch, the volatile memory (3) and clock (
4) A processing method for a battery failure, characterized by clearing the data.
JP61193417A 1986-08-19 1986-08-19 Method for processing battery fault Granted JPS6349861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61193417A JPS6349861A (en) 1986-08-19 1986-08-19 Method for processing battery fault

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61193417A JPS6349861A (en) 1986-08-19 1986-08-19 Method for processing battery fault

Publications (2)

Publication Number Publication Date
JPS6349861A true JPS6349861A (en) 1988-03-02
JPH0373015B2 JPH0373015B2 (en) 1991-11-20

Family

ID=16307615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61193417A Granted JPS6349861A (en) 1986-08-19 1986-08-19 Method for processing battery fault

Country Status (1)

Country Link
JP (1) JPS6349861A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02119730U (en) * 1989-03-10 1990-09-27
JP2009116851A (en) * 2007-10-19 2009-05-28 Denso Corp Microcomputer system
US8046615B2 (en) 2007-10-19 2011-10-25 Denso Corporation Microcomputer system with reduced power consumption
JP2016075681A (en) * 2014-10-06 2016-05-12 イーエム・ミクロエレクトロニク−マリン・エス アー Motor driver device having timepiece motor driver and related component circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02119730U (en) * 1989-03-10 1990-09-27
JP2009116851A (en) * 2007-10-19 2009-05-28 Denso Corp Microcomputer system
JP4535170B2 (en) * 2007-10-19 2010-09-01 株式会社デンソー Microcomputer system
US8046615B2 (en) 2007-10-19 2011-10-25 Denso Corporation Microcomputer system with reduced power consumption
JP2016075681A (en) * 2014-10-06 2016-05-12 イーエム・ミクロエレクトロニク−マリン・エス アー Motor driver device having timepiece motor driver and related component circuit

Also Published As

Publication number Publication date
JPH0373015B2 (en) 1991-11-20

Similar Documents

Publication Publication Date Title
JPS6349861A (en) Method for processing battery fault
JPH03171310A (en) Personal computer
JPS60225923A (en) Information processor
JPH10268981A (en) Device and method for cutting power supply to computer system
JP2540127B2 (en) Programmable controller failure diagnosis device
JPS58169218A (en) Recovery system of break of power supply
JPH01147649A (en) Method for discriminating propriety of back-up memory
JP2816748B2 (en) Power failure compensation type time clock
JPS6247758A (en) Data protecting device for floppy disk
JPS62281781A (en) Monitoring method for accident information
JPH0592855U (en) Information processing equipment
JPH0573183A (en) Power supply and cad/cam for computer
JPH04178855A (en) Personal computer
JPS6026588A (en) Data recorder for elevator
JPS62284440A (en) Software resource maintenance system for terminal equipment
JPS593796A (en) Checking method of data in memory
JPS61226820A (en) Data processing resuming system by power restoration
JPS6247722A (en) Starting method for terminal equipment
JPH02206821A (en) Dual disk device
JPH05233474A (en) Storage contents protection system
JPH0687213B2 (en) Data processing device
JPH0716233U (en) Memory device
JPH0440542A (en) Memory control system
JPS60225193A (en) Electronic unit with fluorescent indicator tube
JPH1011331A (en) Information processing method, information processor, and storage medium

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees