JPS6349815B2 - - Google Patents

Info

Publication number
JPS6349815B2
JPS6349815B2 JP58009882A JP988283A JPS6349815B2 JP S6349815 B2 JPS6349815 B2 JP S6349815B2 JP 58009882 A JP58009882 A JP 58009882A JP 988283 A JP988283 A JP 988283A JP S6349815 B2 JPS6349815 B2 JP S6349815B2
Authority
JP
Japan
Prior art keywords
interrupt
memory
computer
address
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58009882A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59136862A (ja
Inventor
Sumitoshi Saito
Mitsuo Takakura
Tadashi Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58009882A priority Critical patent/JPS59136862A/ja
Publication of JPS59136862A publication Critical patent/JPS59136862A/ja
Publication of JPS6349815B2 publication Critical patent/JPS6349815B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP58009882A 1983-01-26 1983-01-26 マルチコンピユ−タシステムにおける割込み制御装置 Granted JPS59136862A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58009882A JPS59136862A (ja) 1983-01-26 1983-01-26 マルチコンピユ−タシステムにおける割込み制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58009882A JPS59136862A (ja) 1983-01-26 1983-01-26 マルチコンピユ−タシステムにおける割込み制御装置

Publications (2)

Publication Number Publication Date
JPS59136862A JPS59136862A (ja) 1984-08-06
JPS6349815B2 true JPS6349815B2 (de) 1988-10-05

Family

ID=11732521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58009882A Granted JPS59136862A (ja) 1983-01-26 1983-01-26 マルチコンピユ−タシステムにおける割込み制御装置

Country Status (1)

Country Link
JP (1) JPS59136862A (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62243058A (ja) * 1986-04-15 1987-10-23 Fanuc Ltd マルチプロセツサシステムの割込制御方法

Also Published As

Publication number Publication date
JPS59136862A (ja) 1984-08-06

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